FAN6520A_06 Datasheet, PDF (10/15 Pages) Fairchild Semiconductor – Single Synchronous Buck PWM Controller

1.25 times greater than the maximum input voltage. A
voltage rating of 1.5 times is a conservative guideline.
The RMS current rating requirement (I_RMS) for the input
capacitor of a buck regulator is:
I_RMS = I_L (D – D²)
(12)
where the converter duty cycle is
D
=
V-----_O----U---T--
V_IN
.
For a through-hole design, several electrolytic capacitors
may be needed. For surface-mount designs, solid tanta-
lum capacitors can be used, but caution must be exer-
cised with regard to the capacitor’s surge current rating.
The capacitors must be capable of handling the surge
current at power-up. Some capacitor series available
from reputable manufacturers are surge current tested.
Bootstrap Circuit
The bootstrap circuit uses a charge storage capacitor
(C_BOOT) and the internal diode, as shown in Figure 1.
Select these components after the high-side MOSFET
has been chosen. The required capacitance is deter-
mined using the following equation:
CBOOT
=
---------Q-----G-----------
ΔVBOOT
(13)
where Q_G is the total gate charge of the high-side MOS-
FET and ΔV_BOOT is the voltage droop allowed on the
high-side MOSFET drive. To prevent loss of gate drive,
the bootstrap capacitance should be at least 50 times
greater than the C_ISS of Q1.
Thermal Considerations
Total device dissipation:
P_D = P_Q + P_HDRV + P_LDRV
(14)
where P_Q represents quiescent power dissipation.
P_Q = V_CC × [4mA + 0.036 (F_SW – 100)]
(15)
where F_SW is switching frequency (in kHz).
P_HDRV represents internal power dissipation of the upper
FET driver.
P_HDRV = P_H(R) × P_H(F)
(16)
where P_H(R) and P_H(F) are internal dissipations for the
rising and falling edges respectively.
P_H(R)
=
P_Q
1
×
---------------R-----^H---^U----^P----------------
R_HUP + R_E + R_G
(17)
P_H(F)
=
P_Q1
×
---------------R-----^H---^D----^N----------------
R_HDN + R_E + R_G
(18)
where:
P_Q1 = Q_G1 × V_GS(Q1) × F_SW
(19)
where Q_G1 is total gate charge of Q1 for its applied V_GS.
As described in the equations above, the total power
consumed in driving the gate is divided in proportion to
the resistances in series with the MOSFET's internal
gate node, as shown in Figure 9.
BOOT
R_HUP
HDRV
Q1
R_E
R_G
G
R_HDN
S
SW
Figure 9. Driver Dissipation Model
R_G is the polysilicon gate resistance internal to the FET.
R_E is the external gate drive resistor implemented in
many designs. Note that the introduction of R_E can
reduce driver power dissipation, but excess R_E may
cause errors in the “adaptive gate drive” circuitry. For
more information, please refer to Application Note AN-
6003, “Shoot-through” in Synchronous Buck Converters
at http://www.fairchildsemi.com/an/AN/AN-6006.pdf.
P_LDRV is dissipation of the lower FET driver.
P_LDRV = P_L(R) × P_L(F)
(20)
where P_H(R) and P_H(F) are internal dissipations for the
rising and falling edges, respectively:
P_L(R)
=
P_Q2
×
---------------R----^L---^U----^P----------------
R_LUP + R_E + R_G
(21)
P_L(F)
=
P_Q2
×
---------------R-----^L---^D----^N----------------
R_HDN + R_E + R_G
(22)
where:
P_Q2 = Q_G2 × V_GS(Q2) × F_SW.
(23)
Power MOSFET Selection
For more information on MOSFET selection for synchro-
nous buck regulators, refer to: AN-6005: Synchronous
Buck MOSFET Loss Calculations at http://www.fairchild-
semi.com/an/AN/AN-6005.pdf.
Losses in a MOSFET are the sum of its switching (P_SW)
and conduction (P_COND) losses.
In typical applications, the FAN6520A converter's output
voltage is low with respect to its input voltage; therefore
the lower MOSFET (Q2) is conducting the full load cur-
rent for most of the cycle. Choose a MOSFET for Q2 that
has low R_DS(ON) to minimize conduction losses.
In contrast, the high-side MOSFET (Q1) has a much
shorter duty cycle and its conduction loss has less
impact. Q1, however, sees most of the switching losses,
so Q1’s primary selection criteria should be gate charge.
©2005 Fairchild Semiconductor Corporation
FAN6520A Rev. 1.0.5
10
www.fairchildsemi.com