FAN6520A_06 Datasheet, PDF (7/15 Pages) Fairchild Semiconductor – Single Synchronous Buck PWM Controller

Q1
HDRV
SW
Q2
LDRV
Vin
L_OUT
C_IN
+V_OUT
C_OUT
Figure 4. Soft-Start Interval
The FAN6520A incorporates a MOSFET shoot-through
protection method that allows a converter to both sink
and source current. Care should be exercised when
designing a converter with the FAN6520A when it is
known that the converter may sink current.
When the converter is sinking current, it is behaving as a
boost converter regulating its input voltage. This means
that the converter is boosting current into the V_CC rail,
which supplies the bias voltage to the FAN6520A. If this
current has nowhere to go—such as to other distributed
loads on the V_CC rail, through a voltage limiting protec-
tion device, or other methods—the capacitance on the
V_CC bus absorbs the current. This allows the voltage
level of the V_CC rail to increase. If the voltage level of the
rail is boosted to a level that exceeds the maximum volt-
age rating of the FAN6520A, the IC experiences an irre-
versible failure and the converter is no longer
operational. Ensure that there is a path for the current to
follow, other than the capacitance on the rail, to prevent
this failure mode.
Application Information
Layout Considerations
In any high-frequency switching converter, layout is very
important. Switching current from one power device to
another can generate voltage transients across the
impedances of the interconnecting bond wires and circuit
traces. Use wide, short-printed traces to minimize inter-
connecting impedances. The critical components should
be located as close together as possible, using ground
plane construction or single-point grounding.
Figure 5. Printed Circuit Board Power and
Ground Planes or Islands
Figure 5 shows the critical power components of the con-
verter. To minimize voltage overshoot, the interconnect-
ing wires (indicated by heavy lines) should be part of a
ground or power plane in a printed circuit board. The
components shown in Figure 5 should be located as
close together as possible. Note that the capacitors C_IN
and C_OUT may each represent numerous physical capac-
itors. Locate the FAN6520A within two inches of the Q1
and Q2 MOSFETs. The circuit traces for the MOSFETs’
gate and source connections from the FAN6520A must
be sized to handle up to 1A peak current.
Figure 5 shows the circuit traces that require additional
layout consideration. Use single point and ground plane
construction for the circuits shown. Minimize any leakage
current paths on the COMP/OCSET pin and locate the
resistor, R_OSCET, close to the COMP/OCSET pin
because the internal current source is only 20µA. Pro-
vide local V_CC decoupling between the VCC and GND
pins. Locate the capacitor, CBOOT, as close as practical
to the BOOT and PHASE pins. All components used for
feedback compensation should be located as close to
the IC as practical.
Vin
BOOT
Q1
SW
C_BOOT
L_{OUT +VOUT}
+5V
FAN6520A
DBOOT
C_OUT
Q2
VCC
+5V
COMP/OCSET
GND
C_VCC
Figure 6. PCB Small Signal Layout Guidelines
©2005 Fairchild Semiconductor Corporation
FAN6520A Rev. 1.0.5
7
www.fairchildsemi.com