FOD8001R2 Datasheet, PDF (7/12 Pages) Fairchild Semiconductor – High Noise Immunity, 3.3V/5V Logic Gate Optocoupler

Test Circuits
V_DD1 = 3.3V
1
0.1µF
2
0V–3.3V
3
Pulse width = 40ns
Duty Cycle = 50%
4
8
7
0.1µF
V_O
6
C_L
5
V_DD2 = 3.3V
Input
t_PLH
V_IN
t_PHL
3.3V
50%
Output
90%
V_OUT ^10%
t_R
V_OH
50%
V_OL
t_F
Figure 13. Test Circuit for Propogation Delay Time and Rise Time, Fall Time
V_DD1 = 3.3V
1
0.1µF
SW
2
A
B
3
4
+–
V_CM
8
7
0.1µF
V_DD2 = 3.3V
V_O
6
C_L
5
GND
V_OH
V_OL
1kV
V_CM
Switching Pos. (A) V_IN = 3.3V
0.8 x V_DD
0.8V
Switching Pos. (B) V_IN = 0V
CM_H
CM_L
Figure 14. Test Circuit for Instantaneous Common Mode Rejection Voltage
©2008 Fairchild Semiconductor Corporation
FOD8001 Rev. 1.0.3
7
www.fairchildsemi.com