FOD8001R2 Datasheet, PDF (6/12 Pages) Fairchild Semiconductor – High Noise Immunity, 3.3V/5V Logic Gate Optocoupler

Typical Performance Curves (Continued)
Figure 7. Typical Propogation Delay vs. Output Load Capacitance
34
Frequency = 12.5MHz
Duty Cycle = 50%
V_DD1 = V_DD2 = 3.3V
32
30
t
28
PHL
26
t
PL H
24
22
15
20
25
30
35
40
45
50
55
CL - Output Load Capacitance (pF)
Figure 8. Typical Width Distortion vs. Output Load Capacitance
2.6
Frequency = 12.5MHz
Duty Cycle = 50%
2.4 ^{VDD1 = VDD2 = 3.3V}
2.2
2.0
1.8
1.6
1.4
1.2
1.0
15
20
25
30
35
40
45
50
55
C _L - Output Load Capacitance (pF)
Figure 9. Typical Rise Time vs. Output Load Capacitance
12
Frequency = 12.5MHz
Duty Cycle = 50%
11 ^{VDD1 = VDD2 = 3.3V}
10
9
8
7
6
5
4
15
20
25
30
35
40
45
50
55
C_L - Output Load Capacitance (pF)
Figure 10. Typical Fall Time vs. Output Load Capacitance
16
Frequency = 12.5MHz
Duty Cycle = 50%
V_DD1 = V_DD2 = 3.3V
14
12
10
8
6
4
2
15
20
25
30
35
40
45
50
55
C_L - Output Load Capacitance (pF)
Figure 11. Input Supply Current vs. Frequency
6.5
V_DD1 = 5.5V
6.0
5.5
T = 105°C
A
5.0
T = 25°C
A
4.5
T = -40°C
A
4.0
3.5
3.0
0
2000
4000
6000
8000
f - Frequency (kHz)
10000 12000
Figure 12. Output Supply Current vs. Frequency
6.0
V _DD1 = V_DD2 = 5.5V
* Pin 6 Floating
5.8
T = 25°C
A
5.6
T = -40°C
A
5.4
T = 105°C
A
5.2
5.0
0
2000
4000
6000
8000
f - Frequency (kHz)
10000 12000
©2008 Fairchild Semiconductor Corporation
FOD8001 Rev. 1.0.3
6
www.fairchildsemi.com