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FOD8001R2 Datasheet, PDF (2/12 Pages) Fairchild Semiconductor – High Noise Immunity, 3.3V/5V Logic Gate Optocoupler
Pin Definitions
Pin Number
1
2
3
4
5
6
7
8
Pin Name
VDD1
VI
GND1
GND2
VO
NC
VDD2
Pin Function Description
Input Supply Voltage
Input Data
LED Anode – Must be left unconnected
Input Ground
Output Ground
Output Data
Not Connected
Output Supply Voltage
Absolute Maximum Ratings (TA = 25°C Unless otherwise specified.)
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
TSTG
TOPR
TSOL
VDD1, VDD2
VI
II
VO
IO
PDI
PDO
Parameter
Storage Temperature
Operating Temperature
Lead Solder Temperature
(Refer to Reflow Temperature Profile)
Supply Voltage
Input Voltage
Input DC Current
Output Voltage
Average Output Current
Input Power Dissipation(1)(3)
Total Power Dissipation(2)(3)
Value
-40 to +125
-40 to +105
260 for 10 sec
0 to 6.0
-0.5 to VDD1 + 0.5
-10 to +10
-0.5 to VDD2 + 0.5
10
90
70
Units
°C
°C
°C
V
V
µA
V
mA
mW
mW
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
TA
VDD1, VDD2
VIH
VIL
tr, tf
Parameter
Ambient Operating Temperature
Supply Voltages (3.3V Operation)(4)
Supply Voltages (5.0V Operation)(4)
Logic High Input Voltage
Logic Low Input Voltage
Input Signal Rise and Fall Time
Min.
-40
3.0
4.5
2.0
0
Max.
+105
3.6
5.5
VDD
0.8
1.0
Unit
°C
V
V
V
ms
Notes:
1. Derate linearly from 25°C at a rate of tbd W/°C
2. Derate linearly from 25°C at a rate of tbd mW/°C.
3. Functional operation under these conditions is not implied. Permanent damage may occur if the device is subjected
to conditions outside these ratings.
4. 0.1µF bypass capacitor must be connected between Pin 1 and 4, and 5 and 8.
©2008 Fairchild Semiconductor Corporation
FOD8001 Rev. 1.0.3
2
www.fairchildsemi.com