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FOD8001R2 Datasheet, PDF (4/12 Pages) Fairchild Semiconductor – High Noise Immunity, 3.3V/5V Logic Gate Optocoupler
Switching Characteristics (Apply over all recommended conditions, typical value is measured at
VDD1 = VDD2 = +3.3V, VDD1 = +3.3V and VDD2 = +5.0V, VDD1 = +5.0V and VDD2 = +3.3V, VDD1 = VDD2 = +5.0V, TA = 25°C)
Symbol Parameter
Test Conditions
Min. Typ. Max. Unit
tPHL Propagation Delay Time to
Logic Low Output
CL = 15pF
25
40
ns
tPLH Propagation Delay Time to
Logic High Output
CL = 15pF
25
40
ns
PWD
tPSK
tR
tF
|CMH|
|CML|
CPDI
Pulse Width Distortion,
| tPHL – tPLH |
Data Rate
Propagation Delay Skew
Output Rise Time (10%–90%)
Output Fall Time (90%–10%)
Common Mode Transient
Immunity at Output High
Common Mode Transient
Immunity at Output Low
Input Dynamic Power
Dissipation Capacitance(9)
PWD = 40ns, CL = 15pF
CL = 15pF(7)
VI = VDD1, VO > 0.8 VDD1,
VCM = 1000V(8)
VI = 0V, VO < 0.8V,
VCM = 1000V(8)
2
6
ns
25
Mb/s
20
ns
6.5
ns
6.5
ns
20
40
kV/µs
20
40
kV/µs
30
pF
CPDO Output Dynamic Power
Dissipation Capacitance(9)
3
pF
Notes:
7. tPSK is equal to the magnitude of the worst case difference in tPHL and/or tPLH that will be seen between units at any
given temperature within the recommended operating conditions.
8. Common mode transient immunity at output high is the maximum tolerable positive dVcm/dt on the leading edge of
the common mode impulse signal, Vcm, to assure that the output will remain high. Common mode transient immunity
at output low is the maximum tolerable negative dVcm/dt on the trailing edge of the common pulse signal, Vcm, to
assure that the output will remain low.
9. Unloaded dynamic power dissipation is calculated as follows:
CPD x VDD x f + IDD + VPD where f is switched time in MHz.
©2008 Fairchild Semiconductor Corporation
FOD8001 Rev. 1.0.3
4
www.fairchildsemi.com