FAN21SV06_12 Datasheet, PDF (3/17 Pages) Fairchild Semiconductor – TinyBuck™ 6 A, 24V Single-Input Integrated Synchronous Buck Regulator with Synchronization Capability

Pin Configuration
Figure 3. MLP 5x6 mm Pin Configuration (Bottom View)
Pad / Pin Definitions
Pad / Pin
P1, 6-12
P2, 3-5
P3, 21-23
1
2
13
14
15
16
17
18
19
20
24
25
Name
SW
VIN
PGND
BOOT
VIN_Reg
PGOOD
EN
5V_Reg
AGND
ILIM
R_T
FB
COMP
CLK
RAMP
Description
Switching Node. Junction of high-side and low-side MOSFETs.
Power Input Voltage. Supply voltage for the converter.
Power Ground. Power return and Q2 source.
High-Side Drive BOOT Voltage. Connect through capacitor (C_BOOT) to SW. The IC has an
internal synchronous bootstrap diode to recharge the capacitor on this pin to 5 V.
Regulator Input Voltage. Input voltage to the internal regulator. Connect to input voltage
>6.5 V with 1 µF bypass capacitor at the pin.
Power-Good. An open-drain output that pulls LOW when the voltage on the FB pin is
outside the limits specified in the electrical specs. PGOOD does not assert HIGH until the
fault latch is enabled.
ENABLE. Enables operation when pulled to logic HIGH or left open. Toggling EN resets the
regulator after a latched-fault condition. This input has an internal pull-up. When a latched
fault occurs, EN is discharged by a current sink.
5V Regulator Output. Internal regulator output that provides power for the IC’s logic and
analog circuitry. This pin should be connected to AGND through a >2.2 µf X5R/X7R
capacitor.
Analog Ground. The signal ground for the IC. All internal control voltages are referred to
this pin. Tie this pin to the ground island/plane through the lowest impedance connection.
Current Limit. A resistor (R_ILIM) from this pin to AGND can be used to program the current-
limit trip threshold lower than the internal default setting.
Oscillator Frequency and Master/Slave Set. Connecting a resistor (R_T) to AGND sets the
oscillator frequency and configures the CLK pin as an output (master). Tying this pin to
5 V_Reg through a resistor configures the CLK signal as an input (slave) and establishes
the free-running oscillator frequency.
Output Voltage Feedback. Connect through a resistor divider to the output voltage.
Compensation. Error amplifier output. Connect the external compensation network
between this pin and FB.
Clock. Bi-directional signal pin, depending on master/slave configuration. When configured
as a master, this pin represents the clock output that connects directly to the slave(s) for
synchronizing with 180° phase shift.
Ramp Amplitude. A resistor (R_RAMP) connected from this pin to VIN sets the internal ramp
amplitude and also provides voltage feedforward functionality.
© 2006 Fairchild Semiconductor Corporation
FAN21SV06 Rev. 1.0.3
3
www.fairchildsemi.com