FAN21SV06_12 Datasheet, PDF (15/17 Pages) Fairchild Semiconductor – TinyBuck™ 6 A, 24V Single-Input Integrated Synchronous Buck Regulator with Synchronization Capability

Since the FAN21SV06 employs summing current-mode
architecture, Type-2 compensation can be used for
many applications. For applications that require wide
loop bandwidth and/or use very low-ESR output
capacitors, Type-3 compensation may be required.
R_RAMP provides feedforward compensation for changes
in V_IN. With a fixed R_RAMP value, the modulator gain
increases as V_IN is reduced, which could make it difficult
to compensate the loop. For low-input-voltage-range
designs (3 V to 8 V), R_RAMP and the compensation
component values are going to be different as compared
to designs with V_IN between 8 V and 24 V.
Master/Slave Configuration
When first enabled, the IC determines if it is configured as
a master or slave for synchronization, depending on how
R_T is connected.
Table 2. Master / Slave Configuration
R_T to:
GND
5V_Reg
Master / Slave
Master
Slave, free-running
CLK Pin
Output
Input
Slaves free-run in the absence of an external clock signal
input when R_T is connected to 5 V_Reg, allowing
regulation to be maintained. It is not recommended to
leave R_T open when running in slave mode to avoid
noise pick up on the clock pin.
Slave free-running frequency should be set at least 25%
lower than the incoming synchronizing pulse frequency.
Maximum synchronizing clock frequency is recommended
to be below 600 KHz.
Synchronization
The synchronization method employed by the
FAN21SV06 also provides the following features for
maximum flexibility.
 Synchronization to an external system clock
 Multiple FAN21SV06s can be synchronized to a
single master or system clock
 Independently programmable phase adjustment for
one or multiple slaves
 Free-running capability in the absence of system
clock or, if the master is disabled/faulted, the slaves
can continue to regulate at a lower frequency
The FAN21SV06 master outputs an 85ns-wide clock
(CLK) signal, delayed 180^o from its leading PWM edge.
This feature allows out-of-phase operation for the slaves,
thereby reducing the input capacitance requirements
when more than one converter is operating on the same
input supply. The leading SW-node edge is delayed
~40 ns from the rising PWM signal.
On a slave, synchronization is rising-edge triggered. The
CLK input pin has a 1.8 V threshold and a 200 µA current
source pull-up.
In Master mode, the clock signals go out after power-good
signal asserts high. Likewise, in Slave mode
synchronization to an external clock signal occurs after
the power-good signal goes high. Until then, the converter
operates in free-run mode.
Figure 34. Synchronization Timing Diagram
Figure 35. Slave-CLK-Input Block Diagram
One or more slaves can be connected directly to a master
or system clock to achieve a 180^o phase shift.
Figure 36. Slaves with 180^o Phase Shift
Since the synchronizing circuit utilizes a narrow reset
pulse, the actual phase delay is slightly more than 180^o.
The FAN21SV06 is not intended for use in single-output,
multi-phase regulator applications.
PCB Layout
Good PCB layout and careful attention to temperature
rise is essential for reliable operation of the regulator.
Four-layer PCB with 2-ounce copper on the top and
bottom side and thermal vias connecting the layers is
recommended. Keep power traces wide and short to
minimize losses and ringing. Do not connect AGND to
PGND below the IC. Connect AGND pin to PGND at the
output OR to the PGND plane.
Figure 37. Recommended PCB Layout
© 2006 Fairchild Semiconductor Corporation
FAN21SV06 Rev. 1.0.3
15
www.fairchildsemi.com