FAN21SV06_12 Datasheet, PDF (12/17 Pages) Fairchild Semiconductor – TinyBuck™ 6 A, 24V Single-Input Integrated Synchronous Buck Regulator with Synchronization Capability

Circuit Operation
PWM Generation
Refer to Figure 2 for the PWM control mechanism.
FAN21SV06 uses the summing-mode method of control
to generate the PWM pulses. An amplified current-
sense signal is summed with an internally generated
ramp and the combined signal is compared with the
output of the error amplifier to generate the pulse width
to drive the high-side MOSFET. Sensed current from the
previous cycle is used to modulate the output of the
summing block. The output of the summing block is also
compared against a voltage threshold set by the R_LIM
resistor to limit the inductor current on a cycle-by-cycle
basis. The controller facilitates external compensation
for enhanced flexibility.
Initialization
Once VIN_Reg voltage exceeds the UVLO threshold
and EN is high, the IC checks for an open or shorted FB
pin before releasing the internal soft-start ramp (SS).
If R1 is open (Figure 1), error amplifier output (COMP) is
forced LOW and no pulses are generated. After the SS
ramp times out (T1.0), an under-voltage fault occurs.
If the parallel combination of R1 and R_BIAS is ≤ 1 kΩ, the
internal SS ramp is not released and the regulator does
not start.
Internal Regulator
FAN21SV06 facilitates single-supply operation for input
voltages >6.5 V. At startup, the output of the internal
regulator tracks the input voltage and comes into
regulation (5 V) when VIN_Reg exceeds the UVLO
threshold. The EN pin is released at the same time. The
output voltage of the internal regulator (5 V_Reg) is set
to 5 V. The internal regulator supplies power to all the
control circuits including the drivers.
For applications with V_IN<6.5 V, FAN21SV06 can be
used if VIN_Reg is provided with a separate low-power
source >6.5 V. VIN_Reg supply should come up after
VIN during dual-supply operation. The VIN_Reg pin
should always be decoupled with at least 1 µF ceramic
capacitor (see Figure 11).
Since V_CC is used to drive the internal MOSFET gates,
high peak currents are present on the 5V_Reg pin.
Connect a >2.2 µf X5R or X7R decoupling capacitor
between the 5 V_Reg pin and PGND.
In addition to supplying power for the control circuits
internally, 5 V_Reg output can be used as a reference
voltage for other applications requiring low noise
reference voltage. 5 V_Reg is capable of sourcing up to
5 mA of output current.
When EN is pulled LOW externally, 5 V_Reg output is
still present but the IC is in standby mode with no
switching.
Soft-Start
FAN21SV06 uses an internal digital soft-start circuit to
slowly ramp up the output voltage and limit inrush
current during startup. When 5 V_Reg is in regulation
and EN is high, the circuit releases SS and enables the
PWM regulator. Soft-start time is a function of switching
frequency (number of clock cycles).
Once internal SS ramp has charged to 0.8 V (T0.8), the
output voltage is in regulation. Until SS ramp reaches
1.0 V (T1.0), only over-current-protection circuit is active
during soft-start and all other output protections are
inhibited.
In dual-supply operation mode, it is necessary to apply
VIN before VIN_Reg reaches its UVLO threshold to
avoid skipping the soft-start cycle.
Figure 30. Typical Soft-Start Timing Diagram
VIN_Reg UVLO or toggling the EN pin discharges the
SS and resets the IC.
Startup on Pre-Bias
The regulator does not allow the low-side MOSFET to
operate in full synchronous mode until SS reaches 95%
of V_REF (~0.76 V). This enables the regulator to startup
on a pre-biased output and ensures that output is not
discharged during the soft-start cycle.
Protections
The converter output is monitored and protected against
extreme overload, short-circuit, over-voltage, and under-
voltage conditions.
© 2006 Fairchild Semiconductor Corporation
FAN21SV06 Rev. 1.0.3
12
www.fairchildsemi.com