FAN21SV06_12 Datasheet, PDF (13/17 Pages) Fairchild Semiconductor – TinyBuck™ 6 A, 24V Single-Input Integrated Synchronous Buck Regulator with Synchronization Capability

Under-Voltage Protection
If FB remains below the under-voltage threshold for 16
consecutive clock cycles, the fault latch is set and the
converter shuts down. This fault is prevented from
setting the fault latch during soft-start.
Over-Voltage Protection
If FB exceeds 115% • V_REF for two consecutive clock
cycles, the fault latch is set and shutdown occurs.
A shorted high-side MOSFET condition is detected
when SW voltage exceeds ~0.7 V while the low-side
MOSFET is fully enhanced. The fault latch is set
immediately upon detection.
These two fault conditions are allowed to set the fault
latch at any time, including during soft-start.
Over-Temperature Protection
The chip incorporates an over-temperature-protection
circuit that sets the fault latch when a die temperature of
about 155°C is reached. The IC is allowed to restart
when the die temperature falls below 125°C.
EN / Auto-Restart
After a fault, EN pin is discharged with 1 µA current pull
down to a 1.1 V threshold before the internal 800 kΩ pull
up is restored. A new soft-start cycle begins when EN
charges above 1.35 V.
Depending on the external circuit, the FAN21SV06 can
be configured to remain latched off or automatically
restart after a fault, as listed in Table 1.
Table 1. Fault / Restart Configurations
EN pin
Pull to GND
Connected to
5 V_Reg
Open
Cap to GND
Controller / Restart State
Standby
No restart – latched OFF
Immediate restart after fault
New soft-start cycle after:
EN is HIGH (Auto Restart Mode)
With EN left open, restart is immediate.
If auto-restart is not desired, tie the EN pin high with a
logic gate to keep the 1 µA current sink from discharging
EN to 1.1 V. Figure 31 shows one method to pull up EN
to V_CC for a latch configuration.
Figure 31. Enable Control with Latch Option
Power Good (PGOOD) Signal
PGOOD is an open-drain output that asserts LOW when
V_OUT is out of regulation, as measured at the FB pin.
The thresholds are specified in the Electrical
Specifications section. PGOOD does not assert HIGH
until soft start is complete (T1.0).
Application Information
Setting the Output Voltage
The output voltage of the regulator can be set from
0.8 V to ~80% of V_IN by an external resistor divider (R1
and R_BIAS in Figure 1). For output voltages >3.3 V,
output current rating may need to be de-rated depending
on the ambient temperature, power dissipated in the
package and the PCB layout. (Refer to Thermal
Information table and Figure 29.)
The internal reference is set to 0.8 V with 650 nA
sourced from the FB pin to ensure that the regulator
does not start if the pin is left open.
The external resistor divider is calculated using:
0.8V
R_BIAS
=
V_OUT − 0.8V
R1
+ 650nA
(1)
Connect R_BIAS between FB and AGND.
Setting the Clock Frequency
Oscillator frequency is determined by a resistor, R_T, that is
connected between the (R_T)pin and AGND (Master Mode)
or 5 V_Reg (Slave Mode):
10⁶
f_(KHz) = _{(65 • RT ) + 135}
(2)
where R_T is expressed in kΩ.
R_{T (KΩ)}
=
(10⁶
/ f ) − 135
65
(3)
where frequency (f) is expressed in KHz. In slave mode,
the switching frequency is about 10% slower for the
same R_T.
The regulator does not start if R_T is open in Master
mode.
© 2006 Fairchild Semiconductor Corporation
FAN21SV06 Rev. 1.0.3
13
www.fairchildsemi.com