74ABT374_07 Datasheet, PDF (2/13 Pages) Fairchild Semiconductor – Octal D-Type Flip-Flop with 3-STATE Outputs

Connection Diagram
Pin Descriptions
Pin Names
Description
D₀–D₇
CP
Data Inputs
Clock Pulse Input (Active Rising Edge)
OE
3-STATE Output Enable Input
(Active LOW)
O₀–O₇
3-STATE Outputs
Functional Description
The ABT374 consists of eight edge-triggered flip-flops
with individual D-type inputs and 3-STATE true outputs.
The buffered clock and buffered Output Enable are com-
mon to all flip-flops. The eight flip-flops will store the
state of their individual D inputs that meet the setup and
hold time requirements on the LOW-to-HIGH Clock (CP)
transition. With the Output Enable (OE) LOW, the con-
tents of the eight flip-flops are available at the outputs.
When OE is HIGH, the outputs are in a high impedance
state. Operation of the OE input does not affect the state
of the flip-flops.
Logic Diagram
Function Table
Inputs
OE CP D
H HL
H HH
H
L
H
H
L
L
L
H
L HL
L HH
Internal
Q
NC
NC
L
H
L
H
NC
NC
Outputs
O
Function
Z Hold
Z Hold
Z Load
Z Load
L Data Available
H Data Available
NC No Change in
Data
NC No Change in
Data
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
= LOW-to-HIGH Transition
NC = No Change
Please note that this diagram is provided only for the understanding of logic operations and should not be used to
estimate propagation delays.
©1992 Fairchild Semiconductor Corporation
74ABT374 Rev. 1.4
2
www.fairchildsemi.com