FIN3385_12 Datasheet, PDF (17/21 Pages) Fairchild Semiconductor – Low-Voltage, 28-Bit, Flat-Panel Display Link Serializer / Deserializer

AC Loadings and Waveforms (Continued)
Figure 20. Transmitter Output Pulse Bit Position
Figure 21. Receiver Input Bit Position
Figure 22. Receiver LVDS Input Skew Margin
Note:
24. t_RSKM is the budget for the cable skew and source clock skew plus Inter-Symbol Interference (ISI).
The minimum and maximum pulse position values are based on the bit position of each of the seven bits within
the LVDS data stream across PVT (Process, Voltage Supply, and Temperature).
© 2003 Fairchild Semiconductor Corporation
FIN3385 / FIN3386 • Rev. 1.0.6
17
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