FIN3385_12 Datasheet, PDF (13/21 Pages) Fairchild Semiconductor – Low-Voltage, 28-Bit, Flat-Panel Display Link Serializer / Deserializer

Test Circuits
Figure 5. Differential LVDS Output DC Test Circuit
Notes:
A: For all input pulses, t_R or t_F<=1ns.
B: C_L includes all probe and jig capacitance.
Figure 6. Differential Receiver Voltage Definitions, Propagation Delay, and Transition Time Test Circuit
Table 4. Receiver Minimum and Maximum Input Threshold Test Voltages
Applied Voltages (V)
V_IA
V_IB
1.25
1.15
1.15
1.25
2.40
2.30
2.30
2.40
0.10
0
0
0.10
1.50
0.90
0.90
1.50
2.40
1.80
1.80
2.40
0.60
0
0
0.60
Resulting Differential
Input Voltage (mV)
V_ID
100
-100
100
-100
100
-100
600
-600
600
-600
600
-600
Resulting Common
Mode Input Voltage (V)
V_ICM
1.20
1.20
2.35
2.35
0.05
0.05
1.20
1.20
2.10
2.10
0.30
0.30
© 2003 Fairchild Semiconductor Corporation
FIN3385 / FIN3386 • Rev. 1.0.6
13
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