FIN3385_12 Datasheet, PDF (15/21 Pages) Fairchild Semiconductor – Low-Voltage, 28-Bit, Flat-Panel Display Link Serializer / Deserializer

AC Loadings and Waveforms (Continued)
Figure 12. Receiver Setup/Hold and HIGH/LOW Times
Note:
21. For the receiver with falling-edge strobe, the definition of setup/hold time is slightly different from the one with
rising-edge strobe. The clock reference point is the time when the clock falling edge passes through 2V. For hold
time t_RHRC, the clock reference point is the time when falling edge passes through +0.8V.
Figure 13. Transmitter Clock-In to Clock-Out Delay (Rising-Edge Strobe)
Figure 14. Receiver Clock-In to Clock-Out Delay (Falling-Edge Strobe)
Figure 15. Receiver Phase-Lock-Loop Set Time
© 2003 Fairchild Semiconductor Corporation
FIN3385 / FIN3386 • Rev. 1.0.6
15
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