FIN3385_12 Datasheet, PDF (16/21 Pages) Fairchild Semiconductor – Low-Voltage, 28-Bit, Flat-Panel Display Link Serializer / Deserializer

AC Loadings and Waveforms (Continued)
Figure 16. Transmitter Power-Down Delay
Figure 17. Receiver Power-Down Delay
Figure 18. 28 Parallel LVTTL Inputs Mapped to Four Serial LVDS Outputs
Note:
22. The information in this diagram shows the difference between clock out and the first data bit. A 2-bit cycle delay
is guaranteed when the MSB is output from the transmitter.
Figure 19. 21 Parallel LVTTL Inputs Mapped to Three Serial Outputs
Note:
23. This output date pulse position works for both transmitters with 21 TTL inputs, except the LVDS output bit
mapping difference. Two-bit cycle delay is guaranteed with the MSB is output from transmitter.
© 2003 Fairchild Semiconductor Corporation
FIN3385 / FIN3386 • Rev. 1.0.6
16
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