FAN5026_11 Datasheet, PDF (15/17 Pages) Fairchild Semiconductor – Dual DDR / Dual-Output PWM Controller

Q
Q
t_s =
G(SW )
I
DRIVER
= _
G(SW )
V −V
CC
SP

 _{R DRIVER}
+R
GATE

(28)
Most MOSFET vendors specify QGD and QGS. QG(SW)
can be determined as:
Q_{G(SW )} = Q_GD + Q_GS − Q _TH
(29)
where QTH is the gate charge required to get the
MOSFET to it’s threshold (VTH).
For the high-side MOSFET, VDS = VIN, which can be as
high as 20V in a typical portable application. Care
should be taken to include the delivery of the
MOSFET’s gate power (PGATE) in calculating the
power dissipation required for the FAN5026:
P =Q ×V ×f
G ATE
G
CC
SW
(30)
where QG is the total gate charge to reach VCC.
Low-Side Losses
Q2, however, switches on or off with its parallel
Schottky diode conducting, therefore VDS ≈ 0.5V. Since
PSW is proportional to VDS, Q2’s switching losses are
negligible and Q2 is selected based on RDS(ON) only.
Conduction losses for Q2 are given by:
P = (1− D)×I ² × R
(31)
COND
OUT
DS( ON)
where RDS(ON) is the RDS(ON) of the MOSFET at the
highest operating junction temperature, and:
V
D = ^OUT
V
IN
(32)
is the minimum duty cycle for the converter.
Since DMIN < 20% for portable computers, (1-D) ≈ 1
produces a conservative result, further simplifying the
calculation.
The maximum power dissipation (PD(MAX)) is a function of
the maximum allowable die temperature of the low-side
MOSFET; the ΘJA, and the maximum allowable ambient
temperature rise:
T
−T
P
=
D(MAX )
J(MAX )
A (MAX )
Θ _JA
(33)
ΘJA depends primarily on the amount of PCB area that
can be devoted to heat sinking (see Application Note
AN-1029, Maximum Power Enhancement Techniques
for SO-8 Power MOSFETs for SO-8 MOSFET thermal
information).
Layout Considerations
Switching converters, even during normal operation,
produce short pulses of current that could cause
substantial ringing and be a source of EMI if layout
constraints are not observed.
There are two sets of critical components in a DC-DC
converter. The switching power components process
large amounts of energy at high rates and are noise
generators. The low-power components responsible for
bias and feedback functions are sensitive to noise.
A multi-layer printed circuit board is recommended.
Dedicate one solid layer for a ground plane. Dedicate
another solid layer as a power plane and break this
plane into smaller islands of common voltage levels.
Notice all the nodes that are subjected to high-dV/dt
voltage swing; such as SW, HDRV, and LDRV. All
surrounding circuitry tends to couple the signals from
these nodes through stray capacitance. Do not oversize
copper traces connected to these nodes. Do not place
traces connected to the feedback components adjacent
to these traces. It is not recommended to use high-
density interconnect systems, or micro-vias, on these
signals. The use of blind or buried vias should be
limited to the low-current signals only. The use of
normal thermal vias is at the discretion of the designer.
Keep the wiring traces from the IC to the MOSFET gate
and source as short as possible and capable of
handling peak currents of 2A. Minimize the area within
the gate-source path to reduce stray inductance and
eliminate parasitic ringing at the gate.
Locate small critical components, like the soft-start
capacitor and current-sense resistors, as close as
possible to the respective pins of the IC.
The FAN5026 utilizes advanced packaging technology
with lead pitch of 0.6mm. High-performance analog
semiconductors utilizing narrow lead spacing may
require special considerations in design and
manufacturing. It is critical to maintain proper
cleanliness of the area surrounding these devices.
© 2005 Fairchild Semiconductor Corporation
FAN5026 • Rev. 1.0.8
15
www.fairchildsemi.com