FAN5026_11 Datasheet, PDF (10/17 Pages) Fairchild Semiconductor – Dual DDR / Dual-Output PWM Controller

Initialization and Soft Start
Assuming EN is HIGH, FAN5026 is initialized when VCC
exceeds the rising UVLO threshold. Should VCC drop
below the UVLO threshold, an internal power-on reset
function disables the chip.
The voltage at the positive input of the error amplifier is
limited by the voltage at the SS pin, which is charged
with a 5µA current source. Once CSS has charged to
VREF (0.9V) the output voltage is in regulation. The time
it takes SS to reach 0.9V is:
t_0.9
=
0.9 xC_SS
5
(1)
where t0.9 is in seconds if CSS is in µF.
When SS reaches 1.5V, the power-good outputs are
enabled and Hysteretic Mode is allowed. The converter
is forced into PWM Mode during soft-start.
Current Processing Section
The following discussion refers to Figure 12.
The current through the RSENSE resistor (ISNS) is
sampled (typically 400ns) after Q2 is turned on, as
shown in Figure 12. That current is held and summed
with the output of the error amplifier. This effectively
creates a current-mode control loop. The resistor
connected to ISNSx pin (RSENSE) sets the gain in the
current feedback loop. For stable operation, the voltage
induced by the current feedback at the PWM
comparator input should be set to 30% of the ramp
amplitude at maximum load current and line voltage.
The following expression estimates the recommended
value of RSENSE as a function of the maximum load
current (ILOAD(MAX)) and the value of the MOSFET
RDS(ON):
_{ܧܵܰܧܵ}ܴ
=
∙ _{)ܱܰ(ܵܦ}ܴ ∙ _{) ܺܣܯ( ܦܣܱܮ}ܫ4.1 ܭ_{− 100}
30% ∙ 0.125 ∙ ܸ_{) ܺܣܯ(ܰܫ}
(2a)
RSENSE must, however, be kept higher than:
_{ܧܵܰܧܵ}ܴ
=
_{)ܱܰ(ܵܦ}ܴ ∙ _{) ܺܣܯ( ܦܣܱܮ}ܫ
150µܣ
− 100
(2b)
The 100Ω is the internal resistor in series with the
ISNSx pins and has ±15% typical variation. Because
RSENSE is in series with the internal 100Ω resistor, the
gain in the current feedback loop and the current limit
accuracy is affected if RSENSE is close to 100Ω.
Setting the Current Limit
A ratio of ISNS is compared to the current established
when a 0.9V internal reference drives the ILIM pin. The
threshold is determined as follows:
ܵܰܵܫ4
= ܵܰܵܫ ݎ݋ ܯܫܮܫ =12 ∙ ܯܫܮܫ
(3a)
93
Since
^{)ܱܰ(ܵܦܴ ∙ ܦܣܱܮܫ} = ܵܰܵܫ
100 + ܴ_{ܧܵܰܧܵ}
(3b)
and at the ILIM 0.9V threshold:
0.9 10.8
= ܵܰܵܫ12 ∙
=
_{ܯܫܮܫ}ܴ _{ܯܫܮܫ}ܴ
(3c)
therefore:
_{ܦܣܱܮ}ܫ
=
10.8
_{ܯܫܮܫ}ܴ
∙ ^{100 + ܴܧܵܰܧܵ}
_{) ܱܰ( ܵܦ}ܴ
(3d)
Current limit (ILIMIT) should be set high enough to allow
inductor current to rise in response to an output load
transient. Typically, a factor of 1.2 is sufficient. In
addition, since ILIMIT is a peak current cut-off value,
multiply ILOAD(MAX) by the inductor ripple current (e.g.
25%). For example, in Figure 6, the target for ILIMIT:
ILIMIT > 1.2 x 1.25 x 1.6 x 2A ≈ 5A
_{ܯܫܮܫ}ܴ
=
10.8
_{ܶܫܯܫܮ}ܫ
∙ ^{100 + ܴܧܵܰܧܵ}
_{) ܱܰ( ܵܦ}ܴ
(4)
Since the tolerance on the current limit is largely
dependent on the ratio of the external resistors, it is
fairly accurate if the voltage drop on the switching-node
side of RSENSE is an accurate representation of the load
current. When using the MOSFET as the sensing
element, the variation of RDS(ON) causes proportional
variation in the ISNS. This value varies from device to
device and has a typical junction temperature
coefficient of about 0.4%/°C (consult the MOSFET
datasheet for actual values), so the actual current limit
set point decreases proportional to increasing MOSFET
die temperature. A factor of 1.6 in the current limit set
point should compensate for MOSFET RDS(ON)
variations, assuming the MOSFET heat sinking keeps
its operating die temperature below 125°C.
Q2
LDRV
ISNS ^RSENSE
PGND
Figure 11. Improving Current-Sensing Accuracy
More accurate sensing can be achieved by using a
resistor (R1) instead of the RDS(ON) of the FET, as shown
in Figure 11. This approach causes higher losses, but
yields greater accuracy in both VDROOP and ILIMIT. R1 is a
low value resistor (e.g. 10mΩ).
© 2005 Fairchild Semiconductor Corporation
FAN5026 • Rev. 1.0.8
10
www.fairchildsemi.com