FAN5026_11 Datasheet, PDF (13/17 Pages) Fairchild Semiconductor – Dual DDR / Dual-Output PWM Controller

Over-Voltage / Under-Voltage Protection
Should the VSNS voltage exceed 120% of VREF (0.9V)
due to an upper MOSFET failure or for other reasons,
the over-voltage protection comparator forces LDRV
HIGH. This action actively pulls down the output voltage
and, in the event of the upper MOSFET failure,
eventually blows the battery fuse. As soon as the output
voltage drops below the threshold, the OVP comparator
is disengaged.
This OVP scheme provides a ”soft” crowbar function,
which accommodates severe load transients and does
not invert the output voltage when activated —
a common problem for latched OVP schemes.
Similarly, if an output short-circuit or severe load
transient causes the output to drop to less than 75% of
the regulation set point, the regulator shuts down.
Over-Temperature Protection
The chip incorporates an over-temperature protection
circuit that shuts the chip down if a die temperature of
about 150°C is reached. Normal operation is restored at
die temperature below 125°C with internal power-on
reset asserted, resulting in a full soft-start cycle.
Design and Component Selection Guidelines
As an initial step, define the operating input voltage
range, output voltage, and minimum and maximum load
for this example, use:
currents for the controller.
V = 12,V = 2.5
IN
OUT
Setting the Output Voltage
∆I = 25% • 6A = 1.5A
f = 300KHz
(14)
The internal reference voltage is 0.9V. The output is
SW
divided down by a voltage divider to the VSEN pin (for _therefore:
example, R5 and R6 in Figure 5). The output voltage
therefore is:
L ≈ 4.4µH
(15)
0.9V
=
V
OUT
− 0.9V
(10)
R6
R5
To minimize noise pickup on this node, keep the
resistor to GND (R6) below 2K; for example, R6 at
1.82KΩ. Then choose R5:
( ) (1.82KΩ)V − 0.9
R5 =
OUT
= 3.24KΩ
(11)
0.9
For DDR applications converting from 3.3V to 2.5V or
other applications requiring high duty cycles, the duty
cycle clamp must be disabled by tying the converter’s
FPWM to GND. When converter’s FPWM is at GND,
the converter’s maximum duty cycle is greater than
90%. When using as a DDR converter with 3.3V input,
set up the converter for in-phase synchronization by
tying the VIN pin to +5V.
Output Inductor Selection
The minimum practical output inductor value keeps the
inductor current just on the boundary of continuous
conduction at some minimum load. Industry standard
practice is to choose the minimum current somewhere
from 15% to 35% of the nominal current. At light load,
the controller can automatically switch to Hysteretic
Mode to sustain high efficiency. The following equations
select the proper value of the output filter inductor:
∆V
∆I = 2 ×1 = ^OUT
(12)
MIN _ESR
where ∆I is the inductor ripple current and ∆VOUT is the
maximum ripple allowed:
Output Capacitor Selection
The output capacitor serves two major functions in a
switching power supply. Along with the inductor, it filters
the sequence of pulses produced by the switcher and it
supplies the load transient currents. The requirements
are usually dictated by ESR, inductor ripple current (∆I),
and the allowable ripple voltage (∆V):
ESR
<
∆V
∆I
(16)
In addition, the capacitor’s ESR must be low enough to
allow the converter to stay in regulation during a load
step. The ripple voltage due to ESR for the converter in
Figure 6 is 120mVPP. Some additional ripple appears
due to the capacitance value itself:
∆V
=
C_OUT
∆I
× 8 × f_SW
(17)
which is only about 1.5mV for the converter in Figure 6
and can be ignored.
The capacitor must also be rated to withstand the RMS
current, which is approximately 0.3 X (∆I), or about
400mA, for the converter in Figure 6. High-frequency
decoupling capacitors should be placed as close to the
loads as physically possible.
Input Capacitor Selection
The input capacitor should be selected by its ripple
current rating.
V −V
V
L=
IN
f
OUT
× ∆I
×
OUT
V
SW
IN
© 2005 Fairchild Semiconductor Corporation
FAN5026 • Rev. 1.0.8
(13)
13
www.fairchildsemi.com