FAN5026_11 Datasheet, PDF (14/17 Pages) Fairchild Semiconductor – Dual DDR / Dual-Output PWM Controller

Two-Stage Converter Case
In DDR Mode (Figure 5), the VTT power input is
powered by the VDDQ output; therefore all of the input
capacitor ripple current is produced by the VDDQ
converter. A conservative estimate of the output current
required for the 2.5V regulator is:
I =I
+ ^{I VTT}
REGI
VDDQ
2
(18)
As an example, if the average IVDDQ is 3A and average
IVTT is 1A, IVDDQ current is about 3.5A. If average input
voltage is 16V, RMS input ripple current is:
I =I
D − D²
RMS
OUT(MAX )
(19)
where D is the duty cycle of the PWM1 converter and:
D<
V
OUT
= ^2.5
(20)
V 12
IN
therefore:
2
I = 3.5
RMS
2.5
12
−


2.5
12


= 1.42A
(21)
Dual Converter 180° Phased
In Dual Mode (shown in Figure 5), both converters
contribute to the capacitor input ripple current. With
each converter operating 180° out of phase, the RMS
currents add in the following fashion:
I =I
2 _+I
2 _or
(22)
RMS
RMS(1)
RMS(2)
( ) ( ) I_RMS = (I₁)² D₁ − D₁₂ + (I₂ )² D₂ − D₂₂ ⁽²³⁾
which, for the dual 3A converters of Figure 6, calculates:
I = 1.51A
RMS
(24)
(QG). CISS = CGD + CGS and it controls t1, t2, and t4
timing. CGD receives the current from the gate driver
during t3 (as VDS is falling). The gate charge (QG)
parameters on the lower graph are either specified in or
can be derived from MOSFET datasheets.
Assuming switching losses are about the same for both
the rising edge and falling edge, Q1’s switching losses
occur during the shaded time when the MOSFET has
voltage across it and current through it.
These losses are given by:
P_UPPER = P_SW + P_COND
(25)
P
SW
=

V×
DS
2
I
L
× 2 × t_{s } f_SW
(26)
P
V
= ^OUT × I
2 _×R
COND
V_IN
OUT
DS( ON )
(27)
where:
PUPPER is the upper MOSFET’s total losses and PSW
and PCOND are the switching and conduction losses for a
given MOSFET;
RDS(ON) is at the maximum junction temperature (TJ);
and
tS is the switching period (rise or fall time), shown as t2
and t3 in Figure 16.
The driver’s impedance and CISS determine t2, while
t3’s period is controlled by the driver’s impedance and
QGD. Since most of tS occurs when VGS = VSP, use a
constant current assumption for the driver to simplify
the calculation of tS:
V_DS
C_ISS
C_GD
C_ISS
Power MOSFET Selection
Losses in a MOSFET are the sum of its switching (PSW)
and conduction (PCOND) losses.
In typical applications, the FAN5026 converter’s output
voltage is low with respect to its input voltage.
Therefore, the lower MOSFET (Q2) is conducting the
full load current for most of the cycle. Q2 should
therefore be selected to minimize conduction losses,
thereby selecting a MOSFET with low RDS(ON).
In contrast, the high-side MOSFET (Q1) has a much
shorter duty cycle and it’s conduction loss has less
impact. Q1, however, sees most of the switching losses,
the primary selection criteria should be gate charge.
High-Side Losses
Figure 16 shows a MOSFET’s switching interval, with
the upper graph being the voltage and current on the
drain-to-source and the lower graph detailing VGS vs.
time with a constant current charging the gate. The X
axis, therefore, is also representative of gate charge
© 2005 Fairchild Semiconductor Corporation
FAN5026 • Rev. 1.0.8
14
I_D
Q_GS
Q_GD
4.5V
V_SP
V_TH
V_GS
t1
Figure 16.
5V
Q
G(S W )
t2
t3
t4
t5
Switching Losses and QG
VI N
R_D
Figure 17.
C _GD
HDRV
SW
R_GATE
G
C_GS
Drive Equivalent Circuit
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