9020 Datasheet, PDF (15/25 Pages) Fairchild Semiconductor – IGBT Basic II

Fault under load (FUL) is a situation where short-circuit takes place when the device is in on
state, so the V_CE is low before short circuit. In fault under load test circuit, short circuit can
happen with a shoot-through when the IGBT on the opposite side turns on while the DUT
remains turned on. Current rises quickly, and IGBT escapes from complete conduction and
enters the active region. V_CE rises, and i_CG begins to flow in C_CG, which is Miller capacitance.
At this time, if the gate resistance is large, it could rise above V_GG+. Fault current, V_GE=V_GG+,
could rise above the limit for current, and the possibility of device breakdown increases. As
such, it is recommended that low gate resistance be used as a way to guard against “FUL.”
Using low gate resistance would prevent a rise in V_GE during FUL to limit short current. On the
other hand, when short circuit is limited, loss is reduced and short circuit endurance time is
increased. As short circuit endurance time increases, more time would be secured for the pro-
tection circuit to respond. As such, when short circuit is detected through a fault in the sensor
circuit, reducing short current by lowering V_GG+ is a good protection method. Using low value
of resistance R_G is effective in reducing short current, but it has the opposite effects on over-
voltage, dv/dt during turn-off, especially during short circuit, so the value of the resistance
must be set with such trade off in mind.
B. Type II: Hard Switch Fault (HSF)
In this case, short-circuit is caused when the device is turned on from off state with DC link
voltage applied to the device. In such case, di/dt and the value of the fault current are directly
proportional to charging speed of the input capacitance. The fault current can be cut off by
turning off the gate. The amount of the over-voltage created is directly proportional to “DC
loop” inductance and the ratio of the fall in current when the fault current is cut off, which is di/
dt.Since the fault current is significantly greater than the rated current, large value of RG can
be used to prevent the creation of large over-voltage due to di/dt.
Fig. 4. Hard switch fault test circuit6
Fig. 5. Hard switch fault waveform6
V_CE voltage does not change significantly under hard switch fault, so the dv/dt is relatively
smaller than in fault under load. Furthermore, Miller capacitance is small under high voltage.
As such, Miller effect, which is an important issue for fault under load, is less significant under
hard switch fault.
15
Rev. A, April 2002