9020 Datasheet, PDF (11/25 Pages) Fairchild Semiconductor – IGBT Basic II

D. Gate drive layout considerations
a. Effect of gate line inductance on the induced turn-on
Possibility of induced turn-on is greater, as the gate drive impedance is increased during turn-
on and turn-off transient due to stray inductance from the line connected with the gate. As gate
impedance becomes smaller, more current flows through R_G to reduce the charging current of
C_ge, which causes the amount of increase in V_GE to reduce. In order to prevent this, leakage
inductance from DC power supply must be minimized, and R_G should be kept at minimum.
b. Power source stabilizing capacitor
During IGBT switching, current flows to the gate, and at that time, supply voltage of the gate
circuit can oscillate. As a result, the gate drive loss can exceed the designed amount, or it
could reduce the short circuit capability. In such case, it is advised to keep PCB pattern wide
and flat and use enough capacitor for supply voltage stability.
c. Isolation problem
In half bridge topology and similar systems, the upper IGBT gate drive circuits must be insu-
lated from the bottom IGBT circuits. The control board and the gate drive must also be insu-
lated because the upper IGBT emitter free floats as the IGBT switches. As the power DC
voltage rises, the insulating voltage should also rise accordingly. In general, the insulating volt-
age should be at least twice the rated voltage for the IGBT. In addition, care has to be taken
with the noise that comes about from insulating interface. Immunity to noise differs depending
on the how and where the circuits lines are placed, so wiring and placement should be
designed to minimize parasitic capacitance. Parasitic capacitance should be minimized to
reduce C×dv/dt coupling noise between neighboring drive circuits. When using a common
transformer to provide current to both the upper and the lower gate drive, the wire must be
wound to minimize combined capacitance. In using opto-coupler, the opto-coupler must have
insulating capacity with high common mode voltage and transient noise immunity. Upper and
lower, or different types of gate leads of the gate drive must not be wound together.
d. Wiring pattern
G-E
terminals
Fig. 6. Gate drive pattern6
The final push-pull wiring pattern should be short and thick, and if a direct connection between
the gate drive and the IGBT is not possible, then gate wire and the emitter wire could be
twisted to reduce stray inductance. In addition, if the area of the loop that encompasses the
final push-pull stage, the power source pattern, R_G, and G-E terminals of the IGBT is mini-
mized as shown in Fig. 6, effect on the V_GE, from di_C/dt could be minimized when V_GG+ is
injected.
11
Rev. A, April 2002