FXMHD103UMX Datasheet, PDF (13/16 Pages) Fairchild Semiconductor – FXMHD103 HDMI Voltage Translator

Edge Rate Accelerators
The FXMHD103 DDC channel is designed for high-
performance I²C level shifting. Figure 13 shows that
each bi-directional channel contains an Npassgate and
two dynamic drivers. This hybrid architecture is highly
beneficial in an I²C application with large capacitive
loads and where auto-direction is necessary.
For example, during the following I²C protocol events
the bus direction needs to change from “Source-to-Sink”
to “Sink-to-Source” without the occurrence of an edge:
 Clock Stretching
 Slave’s ACK Bit (9th bit=0) following a Master’s
Write Bit (8th bit=0)
 Clock Synchronization and Multi Master Arbitration
If there is an I²C translator between the source and sink
in these examples, the I²C translator must change
direction when both A and C ports are LOW. The
Npassgate can accomplish this efficiently because,
when both A and C ports are LOW, the Npassgate acts
as a low resistive short between the (A and C) ports.
Due to the I²C open-drain topology, I²C drivers are not
push/pull devices. Logic LOWs are “pulled down” (I_sink),
while logic HIGHs are “let go” (3-state). For example,
when the source lets go of SCL (SCL always comes
from the source), the rise time of SCL is largely
determined by the RC time constant, where R=RPU and
C=the bus capacitance. If the FXMHD103 is attached to
the source [on the A port] and there is a source on the C
port, the Npassgate acts as a low-resistive short
between both ports until either of the port’s V_CC/2
thresholds is reached. After the RC time constant has
reached the V_CC/2 threshold of either port, the port’s
edge detector triggers both dynamic drivers to drive
their respective ports in the LOW-to-HIGH (LH)
direction, accelerating the rising edge. The resulting rise
time resembles the scope shot in Figure 14. Effectively,
two distinct slew rates appear in rise time. The first slew
rate (slower) is the RC time constant of the bus. The
second slew rate (much faster) is the dynamic driver
accelerating the edge.
If both the A and C ports of the translator are HIGH, a
high-impedance path exists between the A and C ports
because both the Npassgates are turned off. If a source
or sink device decides to pull SCL or SDA LOW, that
device’s driver pulls down (I_sink) SCL or SDA until the
edge reaches the A or C port V_CC/2 threshold. When
either the A or C port threshold is reached, the port’s
edge detector triggers both dynamic drivers to drive
their respective ports in the HIGH-to-LOW (HL)
direction, accelerating the falling edge.
Driving a Capacitive Load
The FXMHD103 dynamic drivers have enough current
sourcing capability to drive an 800pF capacitive bus.
The Figure 14 scope shot is of an FXMHD103 driving a
lumped load of 600pF. Notice the (30% - 70%) rise time
is only 112ns (R_PU=5KΩ). This is well below the
maximum rise time of 1000ns in Standard Mode
(100KHz) or 300ns in Fast Mode (400KHz).
V_OL vs. V_IL & I_OL
The I²C specification mandates a maximum V_IL (I_OL of
3mA) of V_CC x 0.3
V_OL of 0.4V for an
for an I²C receiver and
I²C transmitter. If there
a maximum
is an HDMI
source on the A port of an I²C translator with
1.8V and an HDMI sink on the I²C translator C
a V_CC of
port with
a V_CC of 5.0V, the maximum V_IL of the source is (1.6V x
0.3) 480mV. Meanwhile, the sink could transmit a valid
logic LOW of 0.4V to the source. 80mV is not very much
margin between the maximum transmitted V_OL of
400mV (HDMI sink) to the maximum received V_IL of
480mV (HDMI source). This appears to be an oversight
in the I²C specification, but there is an explanation. The
I²C specification assumes transmitters and receivers
share the same V_CC. The I²C specification does call out
separate V_OL requirements vs. V_CC conditions where
V_OL1=0.4V when V_CC is > 2.0V and V_OL3=0.2 x V_CC,
when V_CC is < 2.0V. When there is V_CC alignment
between I²C transmitters and receivers, the I²C
specification provides adequate V_IL vs. V_OL margins.
However, when you have a transmitter operating at 5V
and a receiver operating at 1.6V through a translator or
level shifter, the V_OL vs. V_IL margin gets very tight, as in
the above example. Therefore, the voltage drop across
the I²C translator must be as low as possible.
In general, if the I²C translator’s channel resistance is
too high, the voltage drop across the translator could
present a V_IL to a receiver greater than the receiver’s
maximum V_IL. To complicate matters, the I²C
specification states that 6mA of I_OL is recommended for
bus capacitances approaching 400pF in Fast Mode.
More I_OL increases the voltage drop across the I²C
translator. The I²C application benefits when I²C
translators exhibit low V_OL performance. Table 3 depicts
the FXMHD103 targeted V_OL performance vs. V_IL/I_OL
when the direction is from C side to A side, V_CCC=5.0V
and V_CCA=1.6V.
Figure 14. Rise Time Driving 600pF Load
© 2012 Fairchild Semiconductor Corporation
FXMHD103 • Rev. 1.0.2
13
www.fairchildsemi.com