FXMHD103UMX Datasheet, PDF (12/16 Pages) Fairchild Semiconductor – FXMHD103 HDMI Voltage Translator

Application Information
Power Down
The FXMHD103 can be powered down if either
V_CCA or V_CCC equals 0V, or if OE is LOW.
“Hot Plug” Detect Operation
After VCCA and VCCC have powered up to valid
levels, and OE enabled (HIGH) the HPD path is
enabled. The internal 3.3V voltage regulator and
the CEC & DDC blocks are disabled due to the
internal weak pull-down resistor (100kΩ to GND)
on HPD_C. When the HDMI sink recognizes a
valid 5V signal on the HDMI connector, to inform
the HDMI source there is a valid HDMI sink
connected to the HDMI connector; the sink
typically ties the HPD_C signal to the HDMI 5V
supply through a 1KΩ resistor. A HIGH on
HPD_C, in turn, enables the internal voltage
regulator, as well as the DDC & CEC paths. The
HDMI link is active between the HDMI source and
the HDMI sink.
When HPD_C is LOW, the respective resistor pull-
ups (RPUs) on the host and connector sides of the
DDC paths remain coupled to their respective
voltage references. Likewise, when HPD_C is
LOW, the RPUs on the host and connector sides
of the CEC path remain coupled to their respective
voltage references. Since HPD_C disables V_REG
and V_REG is the CEC_C voltage reference, CEC_C
is held to 0V by a weak (50nA) current source
when HPD_C is LOW. This is captured by the
VOUT_DIS parameter.
Backdrive Protection
Backdrive-current protection is available on all
FXMHD103 signals interfacing with the HDMI
connector, including VCCC, SCL_C, SDA_C,
CEC_C, and HPD_C. If the FXMHD103 is
powered down, V_CCA=0V or V_CCC=0V and the
HDMI sink forces 0V – 5V onto any of the HDMI
connector-facing pins (VCCC, SCL_C, SDA_C,
CEC_C & HPD_C). The maximum current flow
from the FXMHD103 is only 5µA, with the
exception of 1.8µA (maximum) on CEC_C.
DDC Channel Description
The HDMI specification implements the Video
Electronics Standards Association (VESA) Display
Data Channel (DDC) for communication between
a single HDMI source and a single HDMI sink. The
DDC is used by the HDMI source to read the
HDMI sink’s Enhanced Extended Display
Identification Data (E-EDID) to discover the sink’s
configuration or capabilities. DDC must meet the
I²C specification, version 2.1, for Standard Mode
devices. Because the HDMI application is meant
for high-definition Transition-Minimized Differential
Signaling (TMDS) video transport across a cable,
the HDMI specification requires the DDC signals
(SCL & SDA) be able to drive a minimum
capacitance of 800pF (source 50pF + cable
assembly 700pF + sink 50pF). The I²C specification
requires a minimum of 400pF capacitance.
Figure 13. DDC Channel Block Diagram, 1 of 2 Channels (SDA & SCL)
© 2012 Fairchild Semiconductor Corporation
FXMHD103 • Rev. 1.0.2
12
www.fairchildsemi.com