FMS6403_05 Datasheet, PDF (13/17 Pages) Fairchild Semiconductor – Triple Video Drivers with Selectable HD/PS/SD/ Bypass Filters for RGB and YPbPr Signals

FMS6403
DATA SHEET
Power Dissipation
TheFMS6403 output drive configuration must be considered
when calculating overall power dissipation. Care must be
taken not to exceed the maximum die junction temperature.
The following example can be used to calculate the
FMS6403’s power dissipation and internal temperature rise.
T_j = T_A + P_d • Θ_JA
where P_d = P_CH1 + P_CH2 + P_CH3
and P_CHx = V_s • I_CH - (V_O2/R_L)
where
V_O = 2V_in + 0.280V
I_CH = (I_CC / 3) + (V_O/R_L)
V_in = RMS value of input signal
I_CC = 90mA
V_s = 5V
R_L = channel load resistance
Board layout can also affect thermal characteristics. Refer to
the Layout Considerations Section for more information.
The FMS6403 is specified to operate with output currents
typically less than 60mA, more than sufficient for a single
(150Ω) video load. Internal amplifiers are current limited
to a maximum of 100mA and should withstand brief dura-
tion short circuit conditions, however this capability is not
guaranteed.
Layout Considerations
General layout and supply bypassing play major roles in
high frequency performance and thermal characteristics.
Fairchild offers a demonstration board, FMS6403DEMO, to
use as a guide for layout and to aid in device testing and
characterization. The FMS6403DEMO is a 4-layer board
with a full power and ground plane. For optimum results,
follow the steps below as a basis for high frequency layout:
• Include 10µF and 0.1µF ceramic bypass capacitors
• Place the 10µF capacitor within 0.75 inches of the
power pin
• Place the 0.1µF capacitor within 0.1 inches of the
power pin
• Connect all external ground pins as tightly as possible,
preferably with a large ground plane under the package
• Layout channel connections to reduce mutual trace
inductance
• Minimize all trace lengths to reduce series inductances.
If routing across a board, place device such that longer
traces are at the inputs rather than the outputs.
If using multiple, low impedance DC coupled outputs, special
layout techniques may be employed to help dissipate heat.
For dual-layer boards, place a 0.5” to 1” (1.27cm to 2.54cm)
square ground plane directly under the device and on the
bottom side of the board. Use multiple vias to connect the
ground planes. For multi-layer boards, additional planes
(connected with vias) can be used for additional thermal
improvements.
Worse case additional die power due to DC loading can be
estimated at (V_CC2/4R_load) per output channel. This assumes
a constant DC output voltage of V_CC2. For 5V V_CC with a
dual DC video load, add 25/(4*75) = 83mW, per channel.
REV. 1C March 2005
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