FMS6403_05 Datasheet, PDF (11/17 Pages) Fairchild Semiconductor – Triple Video Drivers with Selectable HD/PS/SD/ Bypass Filters for RGB and YPbPr Signals

FMS6403
DATA SHEET
includes sync, the EXT_SYNC control input can be set high
and an external sync signal must be input on the SYNC_IN
pin. Refer to the External Sync section for more details. The
timing required for this operating mode is shown in Figure 13.
SYNC timings, T1 and T2, are defined in the SD Electrical
Specifications table on page 2.
0dB Gain 6dB
950mV 1650mV
250mV 250mV
0mV 0mV
Av = 1 (0dB) or 2 (6dB)
Av*700mV
Active
Video
Required Blanking Offset
True Sync Position
NOTE: Tri-level sync may only be compressed 5%. If HD
sync is compressed more than 5% it may not be properly
located.
Sync Timing
Normally, the FMS6403 will respond to bi-level sync and
clamp the sync tip during period ‘B’ in Figure 15(a). When
the filters are switched to high definition mode (30MHz)
or bypass mode the sync processing will respond to tri-level
sync and clamp to the blanking level during period ‘C’ in
Figure 15(b).
NOTE: The diagram indicates SYNC timings at the
output pin.
T1
T2
Allowable SYNC_IN
Figure 13. Bi-Level External
Sync Clamping and Bias
HD and Bypass Mode Video Sync Processing
When the input signal is a high definition signal, the tri-level
sync pulse is too short to allow proper clamp operation.
Rather than clamp during the sync pulse, the sync pulse is
located and the signal is clamped to the blanking level. This
is done in such a way that the sync tip will still be set to
approximately 250mV for signals with 300mV sync tip
amplitude. The EXT_SYNC control input selects the sync
stripper output or the SYNC_IN pin for use by the clamp circuit.
NOTE: The SYNC_IN timing for HD signals is different
than the timing for SD or PS signals.
For HD signals, the SYNC_IN signal must be high when the
clamp must be active. This is during the time immediately
after the sync pulse while the signal is at the blanking level.
This operation is shown in Figure 14. Note that the following
diagrams illustrate DC restore functionality and indicate output
voltage levels for both 0dB and 6dB gain (1V_pp and 2V_pp video
signals at the FMS6403 output pin). SYNC timings, T1 and T2,
are defined in the HD Electrical Specifications table on page 3.
0dB Gain 6dB
1250mV 2250mV
850mV 1450mV
550mV 850mV
250mV 250mV
0mV 0mV
True Sync Position
Allowable SYNC_IN
Av = 1 (0dB) or 2 (6dB)
0H A_v*700mV
Active
Video
Av*300mV
Av*300mV
Required Sync Tip
Offset (Next Sync Tip
Will Be Offset Correctly)
T1
T2
(a) 2250mV
480i and 480p
850mV
250mV
AB
C
(b) 2250mV
1450mV
850mV
250mV
720p, 1080i, 1080p
AB B
C
Figure 15. Sync Timing; Bi-Level (a), Tri-Level (b)
The tri-level sync pulse is located such that the broad pulses
in the vertical interval do not trigger the clamp. In order to
improve the system settling at turn-on, the broad pulses will
be clamped to just above ground. Once the broad pulses (and
tri-level sync tips) are above ground, the normal clamping
process takes over and clamps to the blanking level during
period ‘C’ in Figure 15(b).
The FMS6403 is designed to support the video standards
and associated sync timings shown in Table 1, (additional
standards such as 483p59.94 will also work correctly). The
Filter Settings table from page 9 is repeated on page 12 for
convenience..
Figure 14. Tri-Level Blanking Clamp
REV. 1C March 2005
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