FMS6403_05 Datasheet, PDF (12/17 Pages) Fairchild Semiconductor – Triple Video Drivers with Selectable HD/PS/SD/ Bypass Filters for RGB and YPbPr Signals

DATA SHEET
FMS6403
Filter Settings
F_SEL1, Pin 10
0
0
1
1
F_SEL0, Pin 9
0
1
0
1
Filter -3dB Freq
8MHz
15MHz
32MHz
Filter Bypass
Video Format
SD, 480i
PS, 480p
HD, 1080i, 720p
Unfiltered 1080p
Sync Format
Bi-level, 4.7µs pulse width
Bi-level, 2.35µs pulse width
Tri-level, 589ns pulse width
Tri-level, 290ns, pulse width
Table I
Format
480i
480p
720p
1080i
1080p
Refresh
30Hz
60Hz
60Hz
30Hz
60Hz
Sample Rate
13.5MHz
27MHz
74.25MHz
74.25MHz
148.5MHz
Period (T)
74ns
37ns
13.4ns
13.4ns
6.7ns
A
20T = 1.5µs
20T = 750ns
70T = 938ns
44T = 589ns
44T = 296ns
Note: Timing values are approximate for 30Hz/60Hz refresh rates.
B
64T = 4.7µs
64T = 2.35µs
40T = 536ns
44T = 589ns
44T = 296ns
C
61T = 4.5µs
61T = 2.25µs
220T = 2.95µs
148T = 1.98µs
148T = 996ns
H-Rate
15.75kHz
31.5kHz
45kHz
33.75kHz
67.5kHz
Application Information
Input Circuitry
The DC restore circuit in the FMS6403 requires a source
impedance (R_source = R_s || R_T) of less than or equal to 150Ω
for correct operation. Driving the FMS6403 with a high-
impedance source (e.g. a DAC loaded with 330Ω) will not
yield optimum results. Refer to the Typical Application
Circuit diagram on page 13 for more details.
Output Drive
The FMS6403 is specified to operate with output currents
typically less than 60mA, more than sufficient for a dual
(75Ω) video load. Internal amplifiers are current limited to
approximately 100mA and should withstand brief duration
short circuit conditions, however this capability is not guaranteed.
The maximum specified input voltage of 1.5V_pp can be
sustained for all inputs. When the input is clamped to
1.125V, this does not result in a meaningful output signal.
With a gain of 6dB, the output should be 1.125V ±1.5V
which is not possible since the output cannot drive below
ground. This condition will not damage the part; however,
the output will be clipped. For signals which are clamped to
250mV, this does not occur.
Signals that are at midscale during SYNC (Pb and Pr) must
be clamped to 1.125V and signals that are at their lowest
during SYNC (Y, R, G, B) must be clamped to 250mV for
proper operation. Clamping a Pr signal to 250mV will result
in clipping the bottom of the signal.
The 220uF capacitor coupled with the 150Ω termination, as
shown in the Typical Application Circuit of Figure 5, forms a
high pass filter that blocks the DC while passing the video
frequencies and avoiding tilt. Any value lower than 220µF
will create problems, such as video tilt. Higher values, such
as 470µF - 1000µF are the most optimal output coupling
capacitor. By AC coupling, the average DC level is zero.
Thus, the output voltages of all channels will be centered
around zero.
Sync Recovery
The FMS6403 will typically recover bi-level sync with
amplitude greater than 100mV (33% compressed relative to
the nominal 300mV amplitude). The FMS6403 looks for the
lowest signal voltage and clamps this to approximately
250mV at the output.
Tri-level sync may not be compressed more than 5% (15mV)
for correct operation. Tri-level sync is located by finding the
edges of the tri-level pulse and running a timer to operate the
clamp during the back porch interval.
The selection of the 8MHz or 15MHz filters enables bi-level
sync recovery. Selection of the 30MHz filter or bypass mode
enables tri-level sync recovery. Bi-level and tri-level sync
recovery are not interchangeable. See the detailed sync
processing section for more information.
12
REV. 1C March 2005