FAN3216_12 Datasheet, PDF (13/18 Pages) Fairchild Semiconductor – Dual-2A, High-Speed, Low-Side Gate Drivers

Operational Waveforms
At power-up, the driver output remains LOW until the
V_DD voltage reaches the turn-on threshold. The
magnitude of the OUT pulses rises with VDD until
steady-state V_DD is reached. The non-inverting
operation illustrated in Figure 32 shows that the output
remains LOW until the UVLO threshold is reached, then
the output is in-phase with the input.
The inverting configuration of startup waveforms are
shown in Figure 33. With IN+ tied to VDD and the input
signal applied to IN–, the OUT pulses are inverted with
respect to the input. At power-up, the inverted output
remains LOW until the V_DD voltage reaches the turn-on
threshold, then it follows the input with inverted phase.
Figure 32. Non-Inverting Startup Waveforms
Figure 33. Inverting Startup Waveforms
© 2012 Fairchild Semiconductor Corporation
FAN3216 / FAN3217_F085 • Rev. 1.0.0
13
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