FAN2564_11 Datasheet, PDF (12/13 Pages) Fairchild Semiconductor – 300mA Low VIN LDO for Digital Applications

Physical Dimensions
0.10 C
2X
2.0
A
B
2.0
PIN1
IDENT
TOP VIEW
0.10 C
2X
0.55 MAX
0.10 C
0.08 C 0.05
0.00
SEATING
PLANE
(0.15)
C
SIDE VIEW
PIN1
IDENT
1.50
MAX
1
3
6x
0.35
0.25
1.10
MAX
6
0.65
4
0.35
0.25
6x
1.30
0.10 C A B
0.05 C
BOTTOM VIEW
0.50
1.60
1.50
6
4
1.10
1.40 2.40
1
0.65
3
0.30
RECOMMENDED LAND PATTERN
NOTES:
A. OUTLINE BASED ON JEDEC REGISTRATION
MO-229, VARIATION VCCC.
B. DIMENSIONS ARE IN MILLIMETERS.
C. DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 1994.
D. DRAWING FILENAME: MKT-UMLP06Crev1
Figure 27. 6-Pin, Ultrathin Molded Leadless Package (UMLP)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, spe-
cifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2007 Fairchild Semiconductor Corporation
FAN2564 • Rev. 1.0.2
12
www.fairchildsemi.com