FQS4900 Datasheet, PDF (1/9 Pages) Fairchild Semiconductor – Dual N & P-Channel, Logic Level MOSFET

FQS4900
Dual N & P-Channel, Logic Level MOSFET
August 2000
QFET^TM
General Description
These dual N and P-channel enhancement mode power
field effect transistors are produced using Fairchild’s
proprietary, planar stripe, DMOS technology.
This advanced technology has been especially tailored to
minimize on-state resistance, provide superior switching
performance, and withstand high energy pulse in the
avalanche and commutation mode. This device is well
suited for high interface in telephone sets.
Features
• N-Channel 1.3A, 60V, R_DS(on) = 0.55 Ω @ V_GS = 10 V
R_DS(on) = 0.65 Ω @ V_GS = 5 V
P-Channel -0.3A, -300V, R_DS(on) = 15.5 Ω @ V_GS = -10 V
R_DS(on) = 16 Ω @ V_GS =- 5 V
• Low gate charge ( typical N-Channel 1.6 nC)
( typical P-Channel 3.6 nC)
• Fast switching
• Improved dv/dt capability
D2
D2
D1
D1
5
!
!
4
"!
!
!
6
3
G2
S2
G1
S1
7
!
!
2
$#
!
!
8
1
Absolute Maximum Ratings T_A = 25°C unless otherwise noted
Symbol
V_DSS
I_D
I_DM
V_GSS
dv/dt
P_D
T_J, T_STG
Parameter
Drain-Source Voltage
Drain Current
- Continuous (T_A = 25°C)
- Continuous (T_A = 70°C)
Drain Curent - Pulsed
Gate-Source Voltage
Peak Diode Recovery dv/dt
Power Dissipation (T_A = 25°C)
(T_A = 70°C)
Operating and Storage Temperature Range
(Note 1)
(Note 2)
N-Channel
P-Channel
60
-300
1.3
-0.3
0.82
-0.19
5.2
-1.2
± 20
7.0
4.5
2.0
1.3
-55 to +150
Thermal Characteristics
Symbol
R_θJA
Parameter
Thermal Resistance, Junction-to-Ambient
Typ
Max
--
62.5
Units
V
A
A
A
V
V/ns
W
W
°C
Units
°C/W
©2000 Fairchild Semiconductor International
Rev. A, August 2000