ES25P80 Datasheet, PDF (4/35 Pages) Excel Semiconductor Inc. – 8Mbit CMOS 3.0 Volt Flash Memory with 75Mhz SPI Bus Interface

ADVANCED INFORMATION
EE SS II
Excel Semiconductor inc.
SIGNAL DESCRIPTION
Serial Data Output (SO)
This output signal is used to transfer data serially
out of the device. Data is shifted out on the falling
edge of Serial Clock (SCK).
Serial Data Input (SI)
This input signal is used to transfer data serially into
the device. It receives instructions, addresses, and
the data to be programmed. Values are latched on
the rising edge of Serial Clock (SCK).
Serial Clock (SCK)
This input signal provides the timing of the serial
interface. Instructions, addresses, and data present
at the Serial Data Input (SI) are latched on the ris-
ing edge of Serial Clock (SCK). Data on Serial Data
Output (SO) changes after the falling edge of Serial
Clock (SCK).
Chip Select (CS#)
When this input signal is high, the device is dese-
lected and Serial Data Output (SO) is at high
impedance. Unless an internal Program, Erase or
Write Status Register cycle is in progress, the
device will be in Standby mode. Driving Chip Select
(CS#) Low enables the device, placing it in the
active power mode.
After power-up, a falling edge on Chip Select (CS#)
is required prior to the start of any instruction.
Hold (HOLD#)
The Hold (HOLD#) signal is used to pause any
serial communications with the device without
deselecting the device.
During the Hold instruction, the Serial Data Output
(SO) is high impedance, and Serial Data Input (SI)
and Serial Clock (SCK) are Don’t Care.
To start the Hold condition, the device must be
selected, with Chip Select (CS#) driven Low.
Write Protect (W#)
The main purpose of this input signal is to freeze
the size of the area of memory that is protected
against program or erase instructions (as specified
by the values in the BP2, BP1 and BP0 bits of the
Status Register).
SPI MODES
These devices can be driven by a microcontroller
with its SPI peripheral running in either of the two fol-
lowing modes :
CPOL = 0, CPHA = 0
CPOL = 1, CPHA = 1
For these two modes, input data is latched in on the
rising edge of Serial Clock (SCK), and output data is
available from the falling edge of Serial Clock (SCK).
The difference between the two modes, as shown in
Figure 1, is the clock polarity when the bus master is
in Standby and not transferring data:
SCK remains at 0 for (CPOL = 0, CPHA = 0)
SCK remains at 1 for (CPOL = 1, CPHA = 1)
OPERATING FEATURES
All data into and out of the device is shifted in 8-bit
chunks.
Page Programming
To program one data byte, two instructions are
required : Write Enable (WREN), which is one byte,
and a Page Program (PP) sequence, which consists
of four bytes plus data. This is followed by the inter-
nal program cycle. To spread this overhead, the
Page Program (PP) instruction allows up to 256
bytes to be programmed at a time (changing bits
from 1 to 0), provided that they lie in consecutive
addresses on the same page of memory.
Sector Erase, or Bulk Erase
The Page Program (PP) instruction allows bits to be
programmed from 1 to 0. Before this can be applied,
the bytes of the memory need to be first erased to all
1’s (FFh) before any programming. This can be
achieved in two ways :1) a sector at a time using the
Sector Erase (SE) instruction, or 2) throughout the
entire memory, using the Bulk Erase (BE) instruc-
tion.
ES25P80
4
Rev. 0D May, 11, 2006