ES25P80 Datasheet, PDF (14/35 Pages) Excel Semiconductor Inc. – 8Mbit CMOS 3.0 Volt Flash Memory with 75Mhz SPI Bus Interface

ADVANCED INFORMATION
EE SS II
Excel Semiconductor inc.
Table 4. Protection Modes
W# Signal SRWD Bit
Mode
1
1
1
0
Software
Protected
(SPM)
0
0
Write Protection of the Sta-
tus Register
Protected Area
(See Note)
Status Register is Writable
(if the WREN instruction has
set the WEL bit).
The values in the SRWD,
BP2, BP1 and BP0 bits can
be changed.
Protected against
Page Program and
Erase(SE, BE,PE)
Unprotected Area
(See Note)
Ready to accept Page
Program and Sector
Erase Instructions
Status Register is Hardware
Hardware
write protected.
Protected against
Ready to accept Page
0
1
Protected
The values in the SRWD, Page Program and Program and Sector
(HPM)
BP2, BP1 and BP0 bits can- Erase (SE,BE,PE) Erase Instructions
not be changed
Note:
1. As defined by the values in the Block Protected (BP2, BP1, BP0) bits of the Status Register, as shown in Table 1.
The protection features of the device are summa-
rized in Table 4.
When the Status Register Write Disable (SRWD) bit
of the Status Register is 0 (its initial delivery state),
it is possible to write to the Status Register provided
that the Write Enable Latch (WEL) bit has previ-
ously been set by a Write Enable (WREN) instruc-
tion, regardless of the whether Write Protect (W#) is
driven High or Low.
When the Status Register Write Disable (SRWD) bit
of the Status Register is set to 1, two cases need to
be considered, depending on the state of Write Pro-
tect (W#).
1) If Write Protect (W#) is driven High, it is possible
to write to the Status Register provided that the
Write Enable Latch (WEL) bit has previously been
set by a Write Enable (WREN) instruction.
2) If Write Protect (W#) is driven Low, it is not possi-
ble to write to the Status Register even if the Write
Enable Latch (WEL) bit has previously been set by
a Write Enable (WREN) instruction. (Attempts to
write to the Status Register are rejected, and are
not accepted for execution).
As a consequence, all the data bytes in the memory
area that are software protected (SPM) by the
Block Protect (BP2, BP1, BP0) bits of the Status
Register, are also hardware protected against data
modification.
Regardless of the order of the two events, the
Hardware Protected Mode (HPM) can be entered :
1) by setting the Status Register Write Disable
(SRWD) bit after driving Write Protect (W#) Low
2) or by driving Write Protect (W#) Low after setting
the Status Register Write Disable (SRWD) bit.
The only way to exit the Hardware Protected Mode
(HPM) once entered is to pull Write Protect (W#)
High.
If Write Protect (W#) is permanently tied High, the
Hardware Protected Mode (HPM) can never be
activated, and only the Software Protected Mode
(SPM), using the Block Protect (BP2, BP1, BP0)
bits of the Status Register, can be used.
ES25P80
14
Rev. 0D May, 11, 2006