ES29LV320D Datasheet, PDF (11/59 Pages) Excel Semiconductor Inc. – 32Mbit(4M x 8/2M x 16) CMOS 3.0 Volt-only, Boot Sector Flash Memory

EE SS II
Excel Semiconductor inc.
Start
RESET# =
V_IH or V_ID
Wait 1us
Write 60h to
any address
Write 40h to security
sector address with
A6=0, A1=1,A0=0
Read from security
sector address with
A6=0,A1=1,A0=0
If data=00h, security
sector is unprotected.
If data=01h, security
sector is protected
Remove V_IH or V_ID
from RESET#
Write reset
command
Security sector
Protect Verify
complete
Figure 2. Security Sector Protect Verify
Exit from the Security Sector
Once the Security Sector is locked protected and
verified, the system must write the Exit Security
Sector Region command sequence to return to
reading and writing the remainder of the array.
Caution for the Security Sector Protection
The security sector protection must be used with
caution since, once protected, there is no proce-
dure available for unprotecting the security sector
area and none of the bits in the security sector
memory space can be modified in any way.
HARDWARE DATA PROTECTION
The ES29LV320 device provides some protection
measures against accidental erasure or program-
ming caused by spurious system level signals that
may exist during power transition. During power-
up, all internal registers and latches in the device
are cleared and the device automatically resets to
the read mode. In addition, with its internal state
machine built-in the device, any alteration of the
memory contents or any initiation of new operation
can only occur after successful completion of spe-
cific command sequences. And several features are
incorporated to prevent inadvertent write cycles
resulting from Vcc power-up and power-down transi-
tion or system noise.
Low Vcc Write inhibit
When Vcc is less than V_LKO, the device does not
accept any write cycles. This protects data during
Vcc power-up and power-down. The command reg-
ister and all internal program/erase circuits are dis-
abled, and the device resets to the read mode.
Subsequent writes are ignored until Vcc is greater
than V_LKO. The system must provide proper signals
to the control pins to prevent unintentional writes
when Vcc is greater than V_LKO.
Write Pulse “Glitch” Protection
Noise pulses of less than 5ns (typical) on OE#, CE#
or WE# do not initiate a write cycle.
Logical inhibit
Write cycles are inhibited by holding any one of
OE#=V_IL, CE#=V_IH or WE#=V_IH. To initiate a write
cycle, CE# and WE# must be a logical zero while
OE# is a logical one.
Power-up Write Inhibit
If WE#=CE#=V_IL and OE#=V_IH during power up, the
device does not accept any commands on the rising
edge of WE#. The internal state machine is automat-
ically reset to the read mode on power-up.
ES29LV320D
11
Rev. 2D Jan 5, 2006