XRT71D00_01 Datasheet, PDF (9/26 Pages) Exar Corporation – E3/DS3/STS-1 JITTER ATTENUATOR

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XRT71D00
E3/DS3/STS-1 JITTER ATTENUATOR
REV. 1.2.0
PIN DESCRIPTION
PIN #
26
27
28
29
NAME
RRPOS
VDD
Ch_Addr_0
E3/DS3
(CS)
TYPE
DESCRIPTION
O Receive Positive Data (De-Jittered) Output.
Data which is input via the “RPOS” input pin will be updated on the rising or falling
edge of RRClk (see pin 9), depending upon the state of the ClkES input pin (or bit-field
setting).
*** Digital Positive Supply Voltage: 3.3V or 5.0V ± 5%
I Channel Addr_0 Assignment Input.
This input pin, along with pin 15 permits the user to assign a “Channel Address” to the
XRT71D00.
NOTES:
1. A detailed discussion on “Channel Assignment” is presented in Section _.
2. This input pin is only active whenever the XRT71D00 device has been config-
ured to operate in the “Host” Mode.
I E3/DS3 Select Input/Chip Select Input:
The function of this pin depends on whether the XRT71D00 is configured in Host or
Hardware mode.
Hardware Mode—E3/DS3* Select Input:
This pin along with the STS-1 mode select pin (pin 8) selects the operating mode. A
table relating the settings of these two input pins to the operatintg mode of the
XRT71D00 device is given below.:
STS-1
0
0
1
1
E3/DS3*
0
1
0
1
XRT71D00 Operating Mode
DS3 (44.736 MHz)
E3 (34.368 MHz)
STS-1 (51.84 MHz)
E3 (34.368 MHz)
NOTE: For SONET De-synchronization applications, the user should configure the
XRT71D00 device to operate in the DS3 Mode.
HOST Mode—Chip Select Input:
The local microprocessor must assert this input pin (e.g., set it to “0”) in order to enable
communication with the XRT71D00 device, via the MIcroprocessor Serial Interface.
30
VDD
*** Digital Positive Supply Voltage: 3.3V or 5.0V ± 5%
31
RPOS
I Receive Positive Data (Jittery) Input.
Data that is input on this pin is sampled on either the rising or falling edge of RClk
depending on the setting of the ClkES pin (pin 10). This data will ultimately be output
via the “RRPOS” output pin.
If ClkES is “high”, then RPOS will be sampled on the falling edge of RClk.
If ClkES is “low”, then RPOS will be sampled on the rising edge of RClk.
NOTE: For “Jitter Attenuation” Applications, this pin is typically connected to the
“RPOS” output pin of the corresponding LIU IC.
32
NC
*** This pin is not connected internally.
8