XRT71D00_01 Datasheet, PDF (13/26 Pages) Exar Corporation – E3/DS3/STS-1 JITTER ATTENUATOR

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XRT71D00
E3/DS3/STS-1 JITTER ATTENUATOR
REV. 1.2.0
SYSTEM DESCRIPTION
The XRT71D00 is a fully integrated and self-contained
DS3, E3 and STS-1 Jitter Attenuator IC which was de-
signed to function as either a “Jitter Attenuator” or as a
“Clock Smoother” within SONET De-Synchronizer ap-
plications.
More specifically, the XRT71D00 device was de-
signed to do the following.
1. To attenuate the Jitter (of the incoming clock and
data) such that the user’s system will comply with
the following jitter transfer characteristic require-
ments.
• ETSI TBR-24 (for E3 applications)
• ITU-T G.751 (for E3 applications)
• ITU-T G.752 (for E3 applications)
• ITU-T G.755 (for E3 applications)
• Bellcore GR-499-CORE (Category I to Category
II Interface Jitter Transfer Characteristic require-
ments for DS3 applications).
• Bellcore GR-253-CORE (for SONET STS-1 appli-
cations)
2. To receive the gapped 51.84MHz clock and data
signals, from an “OC-N to DS3 Mapper/De-Map-
per” IC; and to smooth these signals to an “un-
gapped” 44.736MHz clock and data signals. This
particular application is often referred to as a
“SONET De-synchronizer” application. In this
application, the “smoothed” RRCLK and RRPOS
signals could (potentially) be routed to a DS3 LIU
IC, for transmission to a remote terminal equip-
ment, over coaxial cable.
In addition, the XRT71D00 also meets both the “map-
ping” and “pointer adjustment” jitter generation crite-
ria for both Category I and Category II interfaces as
specified in Bellcore GR-253.
The XRT71D00 also meets the DS3 wander specifi-
cation that apply to SONET and asynchronous inter-
faces as specified in the ANSI T1.105.03b 1997 stan-
dard.
Figure 5 presents a simple block diagram of the
XRT71D00 device, when it is configured to operate in
the “Hardware” Mode. Likewise Figure 6 presents a
simple block diagram of the XRT71D00 device, when
it is configured to operate in the “Host” Mode.
FIGURE 5. ILLUSTRATION OF THE XRT71D00 (CONFIGURED TO OPERATE IN THE “HARDWARE” MODE)
BWS
ICT
DJA
RClk
ClkES
RPOS
RNEG
FSS
HOST/HW
Reset
E3/DS3
Jittery
Clock
Timing Control Block /
Phase locked Loop
Smoothed
Clock
Write Clock
Read Clock
16/32 Bit FIFO
MClk
RRClk
RRPOS
RRNEG
FL
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