XRT71D00_01 Datasheet, PDF (22/26 Pages) Exar Corporation – E3/DS3/STS-1 JITTER ATTENUATOR

XRT71D00
E3/DS3/STS-1 JITTER ATTENUATOR
REV. 1.2.0
áç
2.0 OPERATING MODE
2.1 HARDWARE MODE
The HOST/HW pin (pin 12) is used to select the oper-
ating mode of the XRT71D00. In Hardware mode
(connect this pin to ground), the serial processor in-
terface is disabled and hardwired pins are used to
control configuration and report status.
2.1.1 Host Mode:
In Host mode ( connect the HOST/HW pin to VDD),
the serial port interface pins are used to control con-
figuration and status report. In this mode, serial inter-
face pins : SDI, SDO, SClk and CS are used.
A listing of these Command Registers, their Address-
es, and their bit-formats are listed below in Table 6.
TABLE 5: HARDWARE MODE PIN FUNCTIONS
PIN #
PIN NAME
HARDWARE MODE FUNCTION
10
ClkES/(SDI)
ClkES
11
FSS/(SClk)
FSS
15 BWS/Ch_Addr_1
BWS
18
DJA/(SDO)
DJA
28
Ch_Addr_0
None
29
E3/DS3/(CS)
E3/DS3
TABLE 6: ADDRESS AND BIT FORMATS OF THE COMMAND REGISTERS
ADDR
COMMAND
REGISTER
CH_ADDR_1 CH_ADDR_0
TYPE
D7
D6
D5
D4 D3 D2 D1 D0
0X06 CR6
0
0
R/W *** *** STS-1 E3/DS3 DJA BWS ClkES FSS
0x07 CR7
0
0
RO *** ***
***
*** *** *** *** FL
0x0E CR14
0
1
R/W *** *** STS-1 E3/DS3 DJA BWS ClkES FSS
0x0F CR15
0
1
RO *** ***
***
*** *** *** *** FL
0x16 CR22
1
0
R/W *** *** STS-1 E3/DS3 DJA BWS ClkES FSS
0x17 CR22
1
0
RO *** ***
***
*** *** *** *** FL
3.0 MICROPROCESSOR SERIAL INTERFACE
The serial interface for the XRT71D00 and XRT73L00
E3/DS3/STS-1 LIU are the same, which makes it
easy to configure both the XRT71D00 and the LIU
with a single CS, SDI, SDO and SClk input and out-
put pins.
3.1 SERIAL INTERFACE OPERATION.
Serial interface data structure and timings are provid-
ed in Figure 11 and Figure 12 respectively.
The clock signal is provided to the SClk and the CS is
asserted for 50 ns prior to the first rising edge of the
SClk.
3.1.1 Bit Descriptions
3.1.1.1 Bit 1—“R/W” (Read/Write) Bit
This bit will be clocked into the SDI input, on the first
rising edge of SClk (after CS has been asserted).
This bit indicates whether the current operation is a
“Read” or “Write” operation. A “1” in this bit specifies
a “Read” operation, a “0” in this bit specifies a “Write”
operation.
3.1.1.2 Bits 2 through 6
The five (5) bit Address Values (labeled A0, A1, A2
,A3, and A4)
The next four rising edges of the SClk signal will clock
in the 5-bit address value for this particular Read (or
Write) operation. The address selects the Command
Register for reading data from, or writing data to. The
address bits to the SDI input pin is applied in ascend-
ing order with the LSB (least significant bit) first.
Bit 7---A5
A5 must be set to “0”, as shown in Figure 11.
Bit 8—A6
21