XR21V1412IL-0A Datasheet, PDF (9/32 Pages) Exar Corporation – 2-CH FULL-SPEED USB UART

XR21V1412
REV. 1.3.0
2-CH FULL-SPEED USB UART
• Bit 6 is Self-powered mode - set to ’0’ for bus-powered, set to ’1’ for self-powered
• Bit 5 is Remote Wakeup support - set to ’0’ for no support, set to ’1’ for remote wakeup support
• Bit 4:0 are reserved - set to ’0’
1.3.1.4 Device Maximum Power
The Device Maximum Power value replaces the bMaxPower field in the USB Standard Configuration
Descriptor. The value specified is in units of 2 mA. For example, the value 0x2F is decimal 47 or 94 mA. Note
that the default bMaxPower of the V1412 device is 94 mA.
1.4 UART Manager
The UART Manager enables/disables each UART including the TX and RX FIFOs for each UART. The UART
Manager is located in a separate register block from the 2 UART channels.
1.5 UART
There are 2 enhanced UART channels in the V1412. Each UART channel is independent, therefore, they will
need to be initialized and configured independently. Each UART can be configured via USB control transfers
from the USB host. The UART transmitter and receiver sections are described seperately in the following
sections. At power-up, the V1412 will default to 9600 bps, 8 data bits, no parity bit, 1 stop bit, and no flow
control. If a standard CDC driver accesses the V1412, defaults will change. See ”Section 1.2, USB Device
Driver” on page 7.
1.5.1 Transmitter
The transmitter consists of a 128-byte TX FIFO and a Transmit Shift Register (TSR). Once a bulk-out packet
has been received and the CRC has been validated, the data bytes in that packet are written into the TX FIFO
of the specified UART channel. Data from the TX FIFO is transferred to the TSR when the TSR is idle or has
completed sending the previous data byte. The TSR shifts the data out onto the TX output pin at the data rate
defined by the CLOCK_DIVISOR and TX_CLOCK_MASK registers. The transmitter sends the start bit
followed by the data bits (starting with the LSB), inserts the proper parity-bit if enabled, and adds the stop-
bit(s). The transmitter can be configured for 7 or 8 data bits with or without parity or 9 data bits without parity.
If 9 bit data is selected without wide mode, the 9th bit will always be ’0’.
1.5.1.1 Wide Mode Transmit
When both 9 bit data and wide mode are enabled, two bytes of data must be written. The first byte that is
loaded into the TX FIFO are the first 8 bits (data bits 7-0) of the 9-bit data. Bit-0 of the second byte that is
loaded into the TX FIFO is bit-8 of the 9-bit data. The data that is transmitted on the TX pin is as follows: start
bit, 9-bit data, stop bit. Use the WIDE_MODE register to enable wide mode.
1.5.2 Receiver
The receiver consists of a 384-byte RX FIFO and a Receive Shift Register (RSR). Data that is received in the
RSR via the RX pin is transferred into the RX FIFO. Data from the RX FIFO is transferred to the USB host in
response to a Bulk-In request. Depending on the mode, error / status information for that data character may
or may not be stored in the RX FIFO with the data.
1.5.2.1 Normal receive operation with 7 or 8-bit data
Data that is received is stored in the RX FIFO. Any parity, framing or overrun error or break status information
related to the data is discarded. Receive data format is shown in Figure 3.
1.5.2.2 Normal receive operation with 9-bit data
The first 8 bits of data received is stored in the RX FIFO. The 9th bit as well as any parity, framing or overrun
error or break status information related to the data is discarded.
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