XR21V1412IL-0A Datasheet, PDF (25/32 Pages) Exar Corporation – 2-CH FULL-SPEED USB UART

XR21V1412
REV. 1.3.0
2-CH FULL-SPEED USB UART
3.3.14 GPIO_INT_MASK Register Description (Read/Write)
Enables / disables generation of a USB interrupt packet at the change of state of GPIO pins when they are
configured as inputs.
GPIO_INT_MASK[5:0]: GPIOx Interrupt Mask
• Logic 0 = A change on this input causes the device to generate an interrupt packet.
• Logic 1 = A change on this input does not cause the device to generate an interrupt packet.
GPIO_INT_MASK[7:6]: Reserved
These register bits are reserved and should be ’0’.
3.3.15 GPIO_SET Register Description (Read/Write)
Writing a ’1’ in this register drives the GPIO output high. Writing a ’0’ to a bit has no effect. Bits 7-6 are unused
and should be ’0’.
3.3.16 GPIO_CLEAR Register Description (Read/Write)
Writing a ’1’ in this register drives the GPIO output low. Writing a ’0’ to a bit has no effect. Bits 7-6 are unused
and should be ’0’.
3.3.17 GPIO_STATUS Register Description (Read-Only)
This register reports the current state of the GPIO pin.
3.4 UART Custom Registers
TABLE 15: UART CUSTOM REGISTERS
ADDRESS
REGISTER NAME
BIT-7
0X03 UART CHAN A CUSTOM
0
BIT-6
0
BIT-5
0
BIT-4
0
BIT-3
0
BIT-2
0
BIT-1
BIT-0
MaxPkt- WIDE_E
Size
N
0X04 UART CHAN A
LOW_LATENCY
0
0
0
0
0
0
0
EN
0X06 UART CHAN A
CUSTOM_INT_PACKET
0
GPIO5 GPIO4 GPIO3 GPIO0
0
GPIO2 GPIO1
0X0B UART CHAN B CUSTOM
0
0
0
0
0
0
MaxPkt- WIDE_E
Size
N
0X0C UART CHAN B
LOW_LATENCY
0
0
0
0
0
0
0
EN
0X0E UART CHAN B
CUSTOM_INT_PACKET
0
GPIO5 GPIO4 GPIO3 GPIO0
0
GPIO2 GPIO1
3.4.1 CUSTOM Register Description - Chan A / B (Read/Write)
This register enables the Wide mode functionality for the UART.
CUSTOM[0]: Enable wide mode
• Logic 0 = Normal (7, 8 or 9 bit data) mode
• Logic 1 = Wide mode - “Section 1.5.1.1, Wide Mode Transmit” on page 9, “Section 1.5.2.3, Wide mode
receive operation with 7 or 8-bit data” on page 10 and “Section 1.5.2.4, Wide mode receive operation
with 9-bit data” on page 10.
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