XR21V1412IL-0A Datasheet, PDF (10/32 Pages) Exar Corporation – 2-CH FULL-SPEED USB UART

XR21V1412
2-CH FULL-SPEED USB UART
FIGURE 3. NORMAL OPERATION RECEIVE DATA FORMAT
7, 8, or 9 bit data
1^ST byte 7 6 5 4 3 2 1 0 _{7=‘0’ in7bit mode}
REV. 1.3.0
1.5.2.3 Wide mode receive operation with 7 or 8-bit data
Two bytes of data are loaded into the RX FIFO for each byte of data received. The first byte is the received
data. The second byte consists of the error bits and break status. Wide mode receive data format is shown in
Figure 4.
1.5.2.4 Wide mode receive operation with 9-bit data
Two bytes of data are loaded into the RX FIFO for each byte of data received. The first byte is the first 8 bits of
the received data. The 9th bit received is stored in the bit 0 of the second byte. The parity bit is not received /
checked. The remainder of the 2nd byte consists of the framing and overrun error bits and break status.
FIGURE 4. WIDE MODE RECEIVE DATA FORMAT
1st byte
2nd byte
1st byte
2nd byte
7 or 8 bit mode
76543210
x x x x OF B P
9 bit mode
76543210
7 = ‘0’ in 7 bit mode
P = Parity Error (= ‘0’ if not enabled)
B = Break
F = Framing Error
O = Overrun Error
x = ‘0’
x x x x OF B 8
B = Break
F = Framing Error
O = Overrun Error
x = ‘0’
Error flags are also available from the ERROR_STATUS register and the interrupt packet, however these flags
are historical flags indicating that an error has occurred since the previous request. Therefore, no conclusion
can be drawn as to which specific byte(s) may have contained an actual error in this manner.
1.5.3 Rx FIFO Low Latency
In normal operation all bulk-in transfers will be of maxPacketSize (64) bytes to improve throughput and to
minimize host processing. When there are 64 bytes of data in the RX FIFO, the V1412 will acknowledge a
bulk-in request from the host and transfer the data packet. If there is less than 64 bytes in the RX FIFO, the
V1412 may NAK the bulk-in request indicating that data is not ready to transfer at that time. However, if there
is less than 64 bytes in the RX FIFO and no data has been received for more than 3 character times, the
V1412 will acknowledge the bulk-in request and transfer any data in the RX FIFO to the USB host.
In some cases, especially when the baud rate is low, this increases latency unacceptably. The V1412 has a
low latency register bit that will cause the V1412 to immediately transfer any received data in the RX FIFO to
the USB host, i.e. it will not wait for 3 character times. The custom driver can automatically set the
10