XR21V1412IL-0A Datasheet, PDF (22/32 Pages) Exar Corporation – 2-CH FULL-SPEED USB UART

XR21V1412
2-CH FULL-SPEED USB UART
FLOW_CONTROL[2:0]: Flow control mode select
TABLE 13: FLOW CONTROL MODE SELECTION
REV. 1.3.0
MODE
BIT-2 BIT-1 BIT-0
MODE DESCRIPTION
0
0
0
0 No flow control, no address matching.
1
0
0
1 HW flow control enabled. Auto RTS/CTS or DTR/DSR must be selected by
GPIO_MODE.
2
0
1
0 SW flow control enabled
3
0
1
1 Multidrop mode - RX only after address match, TX independent. (Typically
used with GPIO_MODE 3)
4
1
0
0 Multidrop mode - RX / TX only after address match. (Typically used with
GPIO_MODE 4)
FLOW_CONTROL[3]: Half-Duplex Mode
• Logic 0 = Normal (full-duplex) mode. The UART can transmit and receive data at the same time.
• Logic 1 = Half-duplex Mode. In half-duplex mode, any data on the RX pin is ignored when the UART is
transmitting data.
FLOW_CONTROL[7:4]: Reserved
These bits are reserved and should remain ’0’.
3.3.7 XON_CHAR, XOFF_CHAR Register Descriptions (Read/Write)
The XON_CHAR and XOFF_CHAR registers store the XON and XOFF characters, respectively, that are used
in the Automatic Software Flow control. If the V1412 is configured in multidrop mode, the XON_CHAR and
XOFF_CHAR registers are instead used for address matching.
XON_CHAR[7:0]: XON Character
In Automatic Software Flow control mode, the UART will resume data transmission when the XON character
has been received.
For behavior in the Address Match mode, see “Section 1.5.9, Multidrop Mode with address matching” on
page 12.
XOFF_CHAR[7:0]: XOFF Character
In Automatic Software Flow control mode, the UART will suspend data transmission when the XOFF character
has been received.
For behavior in the Address Match mode, see “Section 1.5.9, Multidrop Mode with address matching” on
page 12.
3.3.8 LOOPBACK_CTL Register Descriptions (Read/Write)
LOOPBACK_CTL[0]: Channel
• Logic 0 = UART Channel A
• Logic 1 = UART Channel B
LOOPBACK_CTL[1]: Reserved
This bit is reserved and should remain ’0’.
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