XR21V1412IL-0A Datasheet, PDF (11/32 Pages) Exar Corporation – 2-CH FULL-SPEED USB UART

XR21V1412
REV. 1.3.0
2-CH FULL-SPEED USB UART
RX_FIFO_LOW_LATENCY register bit to force the V1412 to be in the low latency mode, or the user may
manually set this bit. With the CDC-ACM driver, the low latency mode is automatically set whenever the baud
rate is set to a value of less than 46921 bps using the CDC_ACM_IF_SET_LINE_CODING command.
1.5.4 GPIO
Each UART has 6 GPIOs. By hardware default the GPIOs are configured as inputs but may be modified by a
custom driver. Additionally, there are several modes that can be enabled to add additional feature such as
auto RTS/CTS flow control, auto DTR/DSR flow control or auto RS-485 half duplex control. See Table 14.
1.5.5 Automatic RTS/CTS Hardware Flow Control
GPIO5 and GPIO4 of the UART channel can be enabled as the RTS# and CTS# signals for Auto RTS/CTS
flow control when GPIO_MODE[2:0] = ’001’ and FLOW_CONTROL[2:0] = ’001’. Automatic RTS flow control is
used to prevent data overrun errors in local RX FIFO by de-asserting the RTS signal to the remote UART.
When there is room in the RX FIFO, the RTS pin will be re-asserted. Automatic CTS flow control is used to
prevent data overrun to the remote RX FIFO. The CTS# input is monitored to suspend/restart the local
transmitter (see Figure 5):
FIGURE 5. AUTO RTS AND CTS FLOW CONTROL OPERATION
RTSA#
CTSB#
TXB
RXA
Local UART
UARTA
R e c e iv e r F IF O
T rig g e r R e a c h e d
A u to R T S
T rig g e r L e v e l
T ra n s m itte r
A u to C T S
M o n ito r
RXA
RTSA#
TXA
CTSA#
1
2
3
4
ON
ON
6
7
8
5
O FF
OFF
TXB
CTSB#
RXB
RTSB#
9
10
11
R e m o te U A R T
UARTB
T ra n s m itte r
A u to C T S
M o n ito r
R e c e iv e r F IF O
T rig g e r R e a c h e d
A u to R T S
T rig g e r L e v e l
ON
ON
1 ) C O M p o rt o p e n e d , R X F IF O e m p ty , R T S A # o u tp u t is a s s e rte d
2 ) S ig n a l p ro p a g a te d to C T S B # in p u t
3 ) D a ta b y te s e n te r T X F IF O , b e g in tra n s m ittin g o n T X B
4 ) D a ta p ro p a g a te s to R e c e iv in g d e v ic e R X A
5 ) R X F IF O re a c h e s th re s h o ld
6 ) R T S A # d e -a s s e rts
7 ) S ig n a l p ro p a g a te s to C T S B # in p u t
8 ) T ra n s m is s io n s to p s o n T X B
9 ) U S B B u lk -In e m p tie s R X F IF O b e lo w th re s h o ld , R T S A # is a s s e rte d
1 0 ) S ig n a l p ro p a g a te d to C T S B # in p u t
1 1 ) D a ta b y te s re s u m e tra n s m ittin g o n T X B
1.5.6 Automatic DTR/DSR Hardware Flow Control
Auto DTR/DSR hardware flow control behaves the same as the Auto RTS/CTS hardware flow control
described above except that it uses the DTR# and DSR# signals. For Auto hardware flow control,
FLOW_CONTROL[2:0] = ’001’. GPIO3 and GPIO2 become DTR# and DSR#, respectively, when
GPIO_MODE[2:0] = ’010’.
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