XR16L2552IM-F Datasheet, PDF (9/45 Pages) Exar Corporation – 2.25V TO 5.5V DUART WITH 16-BYTE FIFO

REV. 1.1.2
XR16L2552
2.25V TO 5.5V DUART WITH 16-BYTE FIFO
TABLE 2: TXRDY# AND RXRDY# OUTPUTS IN FIFO AND DMA MODE
PINS
FCR BIT-0=0
(FIFO DISABLED)
RXRDY# A/B _{0 = 1 byte.}
1 = no data.
TXRDY# A/B _{0 = THR empty.}
1 = byte in THR.
FCR BIT-0=1 (FIFO ENABLED)
FCR Bit-3 = 0
(DMA Mode Disabled)
0 = at least 1 byte in FIFO
1 = FIFO empty.
0 = FIFO empty.
1 = at least 1 byte in FIFO.
FCR Bit-3 = 1
(DMA Mode Enabled)
1 to 0 transition when FIFO reaches the trigger
level, or timeout occurs.
0 to 1 transition when FIFO empties.
0 = FIFO has at least 1 empty location.
1 = FIFO is full.
2.9 INTA and INTB Ouputs
The INTA and INTB interrupt outputs change according to the operating mode and enahnced features setup.
Table 3 and Table 4 summarize the operating behavior for the transmitter and receiver. Also see Figure 18
through Figure 23.
TABLE 3: INTA AND INTB PINS OPERATION FOR TRANSMITTER
FCR BIT-0 = 0
(FIFO DISABLED)
FCR BIT-0 = 1
(FIFO ENABLED)
INTA/B Pin 0 = a byte in THR
1 = THR empty
0 = at least 1 byte in FIFO
1 = FIFO empty
TABLE 4: INTA AND INTB PIN OPERATION FOR RECEIVER
FCR BIT-0 = 0
(FIFO DISABLED)
INTA/B Pin 0 = no data
1 = 1 byte
FCR BIT-0 = 1
(FIFO ENABLED)
0 = FIFO below trigger level
1 = FIFO above trigger level
2.10 Crystal Oscillator or External Clock Input
The L2552 includes an on-chip oscillator (XTAL1 and XTAL2) to produce a clock for both UART sections in the
device. The CPU data bus does not require this clock for bus operation. The crystal oscillator provides a
system clock to the Baud Rate Generators (BRG) section found in each of the UART. XTAL1 is the input to the
oscillator or external clock buffer input with XTAL2 pin being the output. For programming details, see
“Programmable Baud Rate Generator.”
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