XR16L2552IM-F Datasheet, PDF (42/45 Pages) Exar Corporation – 2.25V TO 5.5V DUART WITH 16-BYTE FIFO

XR16L2552
2.25V TO 5.5V DUART WITH 16-BYTE FIFO
REV. 1.1.2
FIGURE 22. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE DISABLED] FOR CHANNELS A & B
TX FIFO
Empty
TX
(Unloading)
INT*
IER[1]
enabled
TXRDY#
Data in
TX FIFO
Start
Bit
Stop
Bit
S D0:D7 T
S D0:D7 T S D0:D7 T T S D0:D7 T S D0:D7 T
ISR is read
TX FIFO no
longer empty
Last Data Byte
Transmitted
S D0:D7 T
T_SRT
T_WRI
T_SI
TX FIFO
Empty
T_WT
IOW#
(Loading data
into FIFO)
*INT is cleared when the ISR is read or when there is at least one character in the FIFO.
TXDMA#
FIGURE 23. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE ENABLED] FOR CHANNELS A & B
TX FIFO
Empty
TX
(Unloading)
INT*
IER[1]
enabled
TXRDY#
Start
Bit
Stop
Bit
S D0:D7 T
S D0:D7 T S D0:D7 T T S D0:D7 T S D0:D7 T
Last Data Byte
Transmitted
S D0:D7 T
ISR is read
TX FIFO no
longer empty
T_SRT
T_WRI
TX FIFO
Full
T_SI
At least 1
empty location
in FIFO
TX FIFO
Empty
T_WT
IOW#
(Loading data
into FIFO)
*INT is cleared when the ISR is read or when there is at least one character in the FIFO.
TXDMA
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