XRT75L02 Datasheet, PDF (8/50 Pages) Exar Corporation – TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER

xr
REV. 1.0.3
RECEIVE INTERFACE
PIN #
SIGNAL NAME
1
REQEN_0
25
REQEN_1
31
RxON/
SDI
27
RxMON/
SDO
91
RxCLK_0
36
RXCLK_1
92
RPOS_0
35
RPOS_1
XRT75L02
TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER
TYPE
I
I
I
O
O
DESCRIPTION
Receive Equalization Enable Input - Channel 0:
Receive Equalization Enable Input - Channel 1:
Setting this input pin "High" enables the Internal Receive Equalizer of
Channel_n. Setting this pin "Low" disables the Internal Receive Equalizer.
NOTES:
1. This input pin is ignored and should be connected to GND if the
XRT75L02 is operating in the HOST Mode
2. This pin is internally pulled down.
Hardware Mode: Receiver Turn ON Input
Host Mode: Serial Data Input:
Function of this pin depends on whether the XRT75L02 is configured to operate
in Hardware mode or Host mode.
In Hardware mode, setting this input pin “High” turns on and enables the
Receivers of all the channels.
NOTES:
1. If the XRT75L02 is configured in HOST mode, this pin functions as
SDI input pin (please refer to the pin description for Microprocessor
Interface)
2. This pin is internally pulled down.
Hardware Mode: Receive Monitoring Mode
Host Mode: Serial Data Output:
In Hardware mode, when this pin is tied “High” all 2 channels configure into
monitoring channels. In the monitoring mode, the Receiver is capable of moni-
toring the signals with 20 dB flat loss plus 6 dB cable attenuation. This allows
monitoring very weak signal, however the internal LOS circuitry is suppressed
and LOS will never assert nor LOS be declared when operating under this
mode.
In HOST Mode each channel can be independently configured to be a monitor-
ing channel by setting the bits in the channel control registers.
NOTE: If the XRT75L02 is configured in HOST mode, this pin functions as SDO
pin (please refer to the pin description for the Microprocessor Interface).
Receive Clock Output - Channel 0:
Receive Clock Output - Channel 1:
By default, RPOS and RNEG data sampled on the rising edge RxCLK..
Set the RxCLKINV bit or tie RClkINV pin “High” to sample RPOS/RNEG data
on the falling edge of RxCLK
Receive Positive Data Output - Channel 0:
Receive Positive Data Output - Channel 1:
NOTE: If the B3ZS/HDB3 Decoder is enabled in Single-rail mode, then the zero
suppression patterns in the incoming line signal (such as: "00V",
"000V", "B0V", "B00V") is removed and replaced with ‘0’.
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