XRT75L02 Datasheet, PDF (30/50 Pages) Exar Corporation – TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER

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REV. 1.0.3
XRT75L02
TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER
FIGURE 17. INTERFERENCE MARGIN TEST SET UP FOR DS3/STS-1
Sine Wave
N
Generator
Attenuator
DS3 = 22.368 MHz
STS-1 = 25.92 MHz
∑
Pattern Generator ^S
2 ²³ -1 PRBS
Cable Simulator
DUT
XRT75L02
Test Equipment
FIGURE 18. INTERFERENCE MARGIN TEST SET UP FOR E3.
Noise Generator ^N
Attenuator 1
Attenuator 2
Pattern
S
Generator
Cable Simulator
∑
DUT
XRT75L02
Test Equipment
MODE
E3
DS3
STS-1
TABLE 9: INTERFERENCE MARGIN TEST RESULTS
CABLE LENGTH (ATTENUATION)
INTERFERENCE TOLERANCE
0 dB
-14 dB
12 dB
-18 dB
0 feet
-17 dB
225 feet
-16 dB
450 feet
-16dB
0 feet
-16 dB
225 feet
-15 dB
450 feet
-15 dB
5.2 Clock and Data Recovery:
The Clock and Data Recovery Circuit extracts the embedded clock, from the sliced digital data stream and
provides the retimed data to the B3ZS (HDB3) decoder.
The Clock Recovery PLL can be in one of the following two modes:
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