XRT75L02 Datasheet, PDF (35/50 Pages) Exar Corporation – TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER

XRT75L02
TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER
xr
REV. 1.0.3
TABLE 11: JITTER AMPLITUDE VERSUS MODULATION FREQUENCY (JITTER TOLERANCE)
BIT RATE
(KB/S)
STANDARD
INPUT JITTER AMPLITUDE (UI _P-P)
A1
A2
A3
F1(HZ)
MODULATION FREQUENCY
F2(HZ) F3(KHZ) F4(KHZ)
F5(KHZ)
34368 ITU-T G.823 1.5
0.15
-
100
1000
10
800
-
44736
GR-499
5
0.1
-
10
2.3k
60
300
-
CORE Cat I
44736
GR-499
10
0.3
-
10
669
22.3
300
-
CORE Cat II
51840
GR-253
15
1.5
0.15
10
30
300
2
20
CORE Cat II
6.2 JITTER TRANSFER - RECEIVER/TRANSMITTER:
Jitter Transfer function is defined as the ratio of jitter on the output relative to the jitter applied on the input
versus frequency.
There are two distinct characteristics of jitter transfer: i) jitter gain (jitter peaking) defined as the highest ratio
above 0dB; and ii) jitter transfer bandwidth.The overall jitter transfer bandwidth is controlled by a low bandwidth
loop, typically using a voltage-controller crystal oscillator (VCXO).
The jitter transfer function is a ratio between the jitter output and jitter input for a component, or system often
expressed in dB. A negative dB jitter transfer indicates the element removed jitter. A positive dB jitter transfer
indicates the element added jitter. A zero dB jitter transfer indicates the element had no effect on jitter.
Table 12 shows the jitter transfer characteristics and/or jitter attenuation specifications for various data rates:
TABLE 12: JITTER TRANSFER SPECIFICATION/REFERENCES
E3
DS3
STS-1
ETSI TBR-24
GR-499 CORE section 7.3.2
Category I and Category II
GR-253 CORE section 5.6.2.1
The above specifications can be met only with a jitter attenuator that supports E3/DS3/STS-1 rates.
6.3 JITTER GENERATION:
Jitter Generation is defined as the process whereby jitter appears at the output port of the digital equipment in
the absence of applied input jitter. Jitter Generation is measured by sending jitter free data to the clock and
data recovery circuit and measuring the amount of jitter on the output clock or the re-timed data. Since this is
essentially a noise measurement, it requires a definition of bandwidth to be meaningful. The bandwidth is set
according to the data rate. In general, the jitter is measured over a band of frequencies.
6.4 Jitter Attenuator:
An advanced crystal-less jitter attenuator per channel is included in the XRT75L02. The jitter attenuator
requires no external crystal nor high-frequency reference clock.
In Host mode, by clearing or setting the JATx/Rx_n bits in the channel control registers selects the jitter
attenuator either in the Receive or Transmit path on per channel basis. In Hardware mode, JATx/Rx pin selects
globally all three channels either in Receive or Transmit path.
The FIFO size can be either 16-bit or 32-bit. In HOST mode, the bits JA0_n and JA1_n can be set to
appropriate combination to select the different FIFO sizes or to disable the Jitter Attenuator on a per channel
basis. In Hardware mode, appropriate setting of the pins JA0 and JA1 selects the different FIFO sizes or
disables the Jitter Attenuator for all the channels. Data is clocked into the FIFO with the associated clock signal
(TxClk or RxClk) and clocked out of the FIFO with the dejittered clock. When the FIFO is within two bits of
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