XRT75L02 Datasheet, PDF (43/50 Pages) Exar Corporation – TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER

XRT75L02
TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER
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REV. 1.0.3
TABLE 19: REGISTER MAP DESCRIPTION - CHANNEL 0
ADDRESS
(HEX)
REGISTER
TYPE
BIT#
NAME
D0
SYMBOL
DESCRIPTION
DEFAULT
VALUE
JA0_n This bit along with JA1_n bit configures the Jitter
0
Attenuator as shown in the table below.
0x07 (Ch 0) R/W Jitter
0x0F (Ch 1)
Attenuator
JA0_n
0
0
1
1
JA1_n
0
1
0
1
Mode
16 bit FIFO
32 bit FIFO
Disable Jitter
Attenuator
Disable Jitter
Attenuator
0x08
0x10
0x18 -
0x1f
D1 JATx/Rx_n Setting this bit selects the Jitter Attenuator in the
0
Transmit Path. A “0” selects in the Receive Path.
D2
JA1_n This bit along with the JA0_n configures the Jitter
0
Attenuator as shown in the table.
D3 PNTRST_n Setting this bit resets the Read and Write pointers of
0
the jitter attenuator FIFO.
D4 DFLCK_n Set this bit to “1” to disable fast locking of the PLL.
0
This helps to reduce the time for the PLL to lock to
incoming frequency when Jitter Attenuator switches
to narrow band.
D7-D5
Reserved
Reserved
41