XRD98L59 Datasheet, PDF (8/37 Pages) Exar Corporation – CCD Image Digitizers with CDS, PGA and 10-Bit A/D

XRD98L59
SERIAL INTERFACE
The XRD98L59 uses a three wire serial interface (LOAD,
SDI & SCLK) to access the programmable features and
controls of the chip.The serial interface uses a 12-bit shift
register. The first 4 bits shifted in are the address bits, the
next 8 bits are the data bits. The address bits select
which of the internal registers will receive the 8 data bits.
There is no checking or read back of the address bits to
ensure a valid register is written to. If the address bits
select an undefined register, the data will be discarded.
SERIAL PORT PROCEDURES
1) Set LOAD pin low to enable shift register.
2) Shift in 4 address bits (msb first), followed by
8 data bits (msb first).
3) Set LOAD pin high to transfer data from the
shift register to the serial interface register
array.
For optimum image quality, do not run the serial port
during active video. Serial port clocking can couple into
the signal path and degrade accuracy. Also, do not
continuously run SCLK.
Reseting the XRD98L59 is recommended after initial
power-up. It is generally good practice to reset the
XRD98L59 because the serial data may be forced to an
unknown state during power supply cycling by the digital
ASIC.
LOAD
SCLK
t_set
SDI
t_L1
t_SCLK
t_L2
t_hold
MSB
LSB
A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
t1 t2
…
t11 t12 ^Time
Figure 3. Serial Interface Timing Diagram
Rev. 2.00
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