XRD98L59 Datasheet, PDF (14/37 Pages) Exar Corporation – CCD Image Digitizers with CDS, PGA and 10-Bit A/D

XRD98L59
RSTREJ reduces CCD reset noise by disconnecting the
input of the XRD98L59 from the CCD during the CCD
reset pulse. RSTREJ is an internally generated signal.
RSTREJ disconnects the input after the SPIX and before
the SBLK sampling events to reject CCD reset noise.
The RSTREJ switch is always closed (the input is always
connected) if D6=0 in the clock register (address 0011)
of the serial port.
For the timing example shown in Figure 6, SBLK high
samples the pixel black level. The actual hold point of
the pixel black level occurs after a delay of t_BK. t_BK is
the aperture delay of the SBLK timing signal.
The polarities of the SBLK and SPIX signals are indepen-
dently programmable via the serial port.
For the timing example shown in Figure 6, SPIX high
samples the pixel video level. The actual hold point of
the pixel video level occurs after a delay of t_VD. t_VD is
the aperture delay of the SPIX timing signal. The
polarity of the SPIX signal is serial port programmable.
The function of the CDS block, shown in Figure 7, is to
sense the voltage difference between the black level and
video level for each pixel. The CDS and PGA are fully
differential to reject common mode noise. The PGA
output is converted to a single ended signal, and then fed
to the ADC.
REF (CDS non-inverting input) should be connected,
IN
via a capacitor, to the CCD “Common” voltage. This is
typically CCD ground. CCD_IN (CDS inverting input)
should be connected, via a capacitor, to the CCD output
signal. The external coupling capacitors on CCD_IN and
REF_IN should be of equal values to minimize gain errors
(typically 0.01µf +/-10%).
C ^Vout
C
D
GND
External
Coupling
Capacitors
VBIAS2
φ1
RSTREJ
C1
C2
CLAMP
Vbias1 ~0.8
+
PGA1
-
Gain
Register
φ2
+
PGA2
-
C3
C4
+
BUF
-
to ADC
Figure 7. Block Diagram of the CDS, Reset Phase: RSTREJ Switch is Open
Rev. 2.00
14