XRD98L59 Datasheet, PDF (13/37 Pages) Exar Corporation – CCD Image Digitizers with CDS, PGA and 10-Bit A/D

XRD98L59
PIXEL TIMING SBLK & SPIX
The timing required by the XRD98L59 to sample indi-
vidual pixel data from a CCD output is shown below in
Figure 6. The diagram shows the general relationship of
timing signals SBLK and SPIX to the CCD waveform.
The XRD98L59 was designed to sample any analog CCD
waveform. In order to do this the timing signals need to
be referenced to the waveform itself, not to the CCD’s
timing generator.
Reset
Reject
Switch
Open
CCD_IN
RST REJ* ¹
Reset
Phase
Reset
Pulse
t_PIX
Pixel N
Black
Reference
Phase
Reset
Reject
Switch
Closed
Video
Phase
t_RST
2
t_BK
t_VD
pixel black level
sample point
Pixel N + 1
pixel video level
sample point
1
t_PW2
2
SBLK
SPIX
DB[9:0]
3
N-4
t_PW1
5
4
t_DL
3
N-3
5
4
t_DL
Figure 6. CDS Timing Diagram - Proper Placement of Timing is
Critical to Image Quality, SDI=0011 0100 1100
*RST REJ is an internally generated signal.
Event
1
2
3
4
5
Action
↑ RSTREJ
Disconnects CDS Inputs from Reset Noise
↓ RSTREJ
Connects CDS Inputs
SBLK High
Sample Black Level
SPIX High
Sample Video Level
SBLK/SPIX Low Hold Video and Black Level
Table 12. Event Table for CDS Timing (SDI=0011 0100 1100)
Rev. 2.00
13