XRD98L59 Datasheet, PDF (15/37 Pages) Exar Corporation – CCD Image Digitizers with CDS, PGA and 10-Bit A/D

XRD98L59
During the reset phase of each pixel the RSTREJ
switches are turned off, see Figure 7, opening the
XRD98L59 CDS input. This is done to limit reset pulse
transients seen by the front end of the XRD98L59.
During the black reference phase of each pixel the
RSTREJ switches are closed, allowing the difference
between the black reference level voltage and VBIAS2
to develop across capacitors C1 and C2 (see Figure 8).
φ1 is closed when SBLK is active.
C ^Vout
C
D _GND
External
Coupling
Capacitors
In_Pos
VBIAS2
φ1
RSTREJ
C1
In_Neg
C2
CLAMP
Vbias1 ~0.8
+
PGA1
-
Gain
Register
φ2
+
PGA2
-
C3
C4
+
BUF
-
to ADC
Figure 8. CDS - Black Reference Phase: RSTREJ and φ1 Switch Closed
During the video phase of each pixel the φ2 switches are
closed when SPIX is active. The difference between the
pixel black reference level and video level is transmitted
through capacitors C1 & C2. Differential amplifier PGA1
amplifies both CDS inputs from CCD_IN and REF_IN. The
inactive phase of SPIX turns off the φ2 switches, storing
the differential pixel value on capacitors C3 & C4 (see
Figure 9).
C ^Vout
C
D _GND
External
Coupling
Capacitors
VBIAS2
φ1
RSTREJ
C1
C2
CLAMP
Vbias1~0.8
+
PGA1
-
Gain
Register
φ2
C3
+
PGA2
-
C4
+
BUF
-
to ADC
Figure 9. CDS - Video Phase: φ1 Switches Open, φ2 and RSTREJ Switches Closed
Rev. 2.00
15